nextpnr/himbaechel/uarch/gowin
YRabbit 7f58300928 Gowin. Taking into account the features of ROM
For pROM(X9) primitives in images generated by Gowin IDE, there is an
interesting recommunication of inputs depending on the data bit depth.
For example, in some cases, a high logical level may be applied to the
Write Enable input, which, let’s say, is not entirely usual for Read
Only memory.

Here we will do similar manipulations.

In addition, several minor bug fixes are included:

 - Fixed bit numbering for non-X9 series primitives.
 - Fixed decoder generation for BLKSEL - do not assume unused inputs are
   connected to GND.
 - Use default values for BSRAM parameters - don't assume their
   mandatory presence.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2024-07-04 19:10:07 +10:00
..
CMakeLists.txt gowin: Himbaechel. Add GW1NZ-1 BSRAM. 2023-11-26 13:08:09 +01:00
constids.inc Gowin. Fix BSRAM block selection. 2024-07-03 15:09:13 +02:00
cst.cc gowin: Himbaechel. Extend clock router 2023-09-08 09:15:35 +02:00
cst.h gowin: Himbaechel. Add constraint file processing. 2023-08-31 08:28:09 +02:00
globals.cc gowin: Add support for DSP primitives. 2024-03-22 09:47:10 +00:00
globals.h gowin: Himbaechel. Add a clock router. 2023-08-31 08:28:09 +02:00
gowin_arch_gen.py Gowin. Fix BSRAM block selection. 2024-07-03 15:09:13 +02:00
gowin_utils.cc Gowin. Fix BSRAM block selection. 2024-07-03 15:09:13 +02:00
gowin_utils.h Gowin. Fix BSRAM block selection. 2024-07-03 15:09:13 +02:00
gowin.cc Gowin. Add fix for Single Port BSRAM 2024-06-25 11:14:02 +02:00
gowin.h Gowin. Fix BSRAM block selection. 2024-07-03 15:09:13 +02:00
pack.cc Gowin. Taking into account the features of ROM 2024-07-04 19:10:07 +10:00
pack.h gowin: Himbaechel. Add ALU. 2023-08-31 08:28:09 +02:00