10 lines
214 B
Verilog
10 lines
214 B
Verilog
module top(input clk, cen, rst, ina, inb, output outa, outb, outc, outd);
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reg [15:0] ctr = 0;
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always @(posedge clk)
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ctr <= ctr + 1'b1;
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assign {outa, outb, outc, outd} = ctr[15:12];
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endmodule
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