132 lines
2.2 KiB
Verilog
132 lines
2.2 KiB
Verilog
module blinky (
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input clk_pin,
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output led1_pin,
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output led2_pin,
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output led3_pin,
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output led4_pin,
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output led5_pin
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);
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wire clk, led1, led2, led3, led4, led5;
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(* BEL="13_12_io1" *)
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SB_IO #(
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.PIN_TYPE(6'b 0110_01),
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.PULLUP(1'b0),
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.NEG_TRIGGER(1'b0)
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) led1_iob (
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.PACKAGE_PIN(led1_pin),
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.LATCH_INPUT_VALUE(),
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.CLOCK_ENABLE(),
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.INPUT_CLK(),
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.OUTPUT_CLK(),
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.OUTPUT_ENABLE(),
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.D_OUT_0(led1),
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.D_OUT_1(),
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.D_IN_0(),
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.D_IN_1()
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);
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(* BEL="13_12_io0" *)
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SB_IO #(
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.PIN_TYPE(6'b 0110_01),
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.PULLUP(1'b0),
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.NEG_TRIGGER(1'b0)
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) led2_iob (
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.PACKAGE_PIN(led2_pin),
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.LATCH_INPUT_VALUE(),
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.CLOCK_ENABLE(),
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.INPUT_CLK(),
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.OUTPUT_CLK(),
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.OUTPUT_ENABLE(),
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.D_OUT_0(led2),
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.D_OUT_1(),
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.D_IN_0(),
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.D_IN_1()
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);
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(* BEL="13_11_io1" *)
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SB_IO #(
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.PIN_TYPE(6'b 0110_01),
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.PULLUP(1'b0),
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.NEG_TRIGGER(1'b0)
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) led3_iob (
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.PACKAGE_PIN(led3_pin),
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.LATCH_INPUT_VALUE(),
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.CLOCK_ENABLE(),
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.INPUT_CLK(),
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.OUTPUT_CLK(),
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.OUTPUT_ENABLE(),
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.D_OUT_0(led3),
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.D_OUT_1(),
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.D_IN_0(),
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.D_IN_1()
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);
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(* BEL="13_11_io0" *)
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SB_IO #(
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.PIN_TYPE(6'b 0110_01),
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.PULLUP(1'b0),
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.NEG_TRIGGER(1'b0)
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) led4_iob (
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.PACKAGE_PIN(led4_pin),
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.LATCH_INPUT_VALUE(),
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.CLOCK_ENABLE(),
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.INPUT_CLK(),
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.OUTPUT_CLK(),
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.OUTPUT_ENABLE(),
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.D_OUT_0(led4),
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.D_OUT_1(),
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.D_IN_0(),
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.D_IN_1()
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);
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(* BEL="13_9_io1" *)
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SB_IO #(
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.PIN_TYPE(6'b 0110_01),
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.PULLUP(1'b0),
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.NEG_TRIGGER(1'b0)
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) led5_iob (
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.PACKAGE_PIN(led5_pin),
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.LATCH_INPUT_VALUE(),
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.CLOCK_ENABLE(),
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.INPUT_CLK(),
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.OUTPUT_CLK(),
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.OUTPUT_ENABLE(),
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.D_OUT_0(led5),
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.D_OUT_1(),
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.D_IN_0(),
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.D_IN_1()
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);
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(* BEL="0_8_io1" *)
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SB_IO #(
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.PIN_TYPE(6'b 0000_01),
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.PULLUP(1'b0),
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.NEG_TRIGGER(1'b0)
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) clk_iob (
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.PACKAGE_PIN(clk_pin),
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.LATCH_INPUT_VALUE(),
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.CLOCK_ENABLE(),
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.INPUT_CLK(),
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.OUTPUT_CLK(),
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.OUTPUT_ENABLE(),
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.D_OUT_0(),
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.D_OUT_1(),
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.D_IN_0(clk),
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.D_IN_1()
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);
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localparam BITS = 5;
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localparam LOG2DELAY = 22;
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reg [BITS+LOG2DELAY-1:0] counter = 0;
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reg [BITS-1:0] outcnt;
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always @(posedge clk) begin
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counter <= counter + 1;
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outcnt <= counter >> LOG2DELAY;
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end
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assign {led1, led2, led3, led4, led5} = outcnt ^ (outcnt >> 1);
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endmodule
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