131 lines
2.8 KiB
C++
131 lines
2.8 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef DESIGN_H
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#define DESIGN_H
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#include <assert.h>
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#include <stdint.h>
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#include <string>
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#include <unordered_map>
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#include <unordered_set>
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#include <vector>
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// replace with proper IdString later
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typedef std::string IdString;
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// replace with haslib later
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template <typename T> using pool = std::unordered_set<T>;
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template <typename T, typename U> using dict = std::unordered_map<T, U>;
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using std::vector;
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struct GraphicElement
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{
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// This will control colour, and there should be separate
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// visibility controls in some cases also
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enum
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{
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// Wires entirely inside tiles, e.g. between switchbox and bels
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G_LOCAL_WIRES,
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// Standard inter-tile routing
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G_GENERAL_WIRES,
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// Special inter-tile wires, e.g. carry chains
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G_DEDICATED_WIRES,
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G_BEL_OUTLINE,
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G_SWITCHBOX_OUTLINE,
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G_TILE_OUTLINE,
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G_BEL_PINS,
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G_SWITCHBOX_PINS,
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G_BEL_MISC,
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G_TILE_MISC,
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} style;
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enum
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{
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G_LINE,
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G_BOX,
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G_CIRCLE,
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G_LABEL
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} type;
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float x1, y1, x2, y2, z;
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std::string text;
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};
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#include "chip.h"
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struct CellInfo;
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struct PortRef
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{
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CellInfo *cell = nullptr;
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IdString port;
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};
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struct NetInfo
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{
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IdString name;
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PortRef driver;
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vector<PortRef> users;
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dict<IdString, std::string> attrs;
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// wire -> uphill_pip
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dict<WireId, PipId> wires;
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};
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enum PortType
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{
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PORT_IN = 0,
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PORT_OUT = 1,
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PORT_INOUT = 2
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};
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struct PortInfo
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{
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IdString name;
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NetInfo *net;
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PortType type;
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};
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struct CellInfo
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{
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IdString name, type;
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dict<IdString, PortInfo> ports;
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dict<IdString, std::string> attrs, params;
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BelId bel;
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// cell_port -> bel_pin
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dict<IdString, IdString> pins;
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};
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struct Design
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{
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struct Chip chip;
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Design(ChipArgs args) : chip(args)
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{
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// ...
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}
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dict<IdString, NetInfo *> nets;
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dict<IdString, CellInfo *> cells;
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};
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#endif
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