YRabbit 4d1de4532a Gowin. BUGFIX. Create all Clock Pips. (#1358) ... Some Clocks PIPS were not created due to a check for the presence of a delay class, now all wires are attributed to the class so that there is no longer any need for this check. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>		2024-09-05 21:39:26 +01:00
..
CMakeLists.txt	gowin: Himbaechel. Add GW1NZ-1 BSRAM.	2023-11-26 13:08:09 +01:00
constids.inc	Gowin. Implement the UserFlash primitive (#1357)	2024-09-04 11:55:35 +01:00
cst.cc	Himbaechel Gowin: HCLK Support (#1340)	2024-08-03 15:57:22 +02:00
cst.h	gowin: Himbaechel. Add constraint file processing.	2023-08-31 08:28:09 +02:00
globals.cc	Himbaechel Gowin: HCLK Support (#1340)	2024-08-03 15:57:22 +02:00
globals.h	gowin: Himbaechel. Add a clock router.	2023-08-31 08:28:09 +02:00
gowin_arch_gen.py	Gowin. BUGFIX. Create all Clock Pips. (#1358)	2024-09-05 21:39:26 +01:00
gowin_utils.cc	Himbaechel Gowin: HCLK Support (#1340)	2024-08-03 15:57:22 +02:00
gowin_utils.h	Himbaechel Gowin: HCLK Support (#1340)	2024-08-03 15:57:22 +02:00
gowin.cc	himbaechel/gowin: add timing information	2024-08-21 10:58:55 +01:00
gowin.h	Gowin. Implement the UserFlash primitive (#1357)	2024-09-04 11:55:35 +01:00
pack.cc	Gowin. Implement the UserFlash primitive (#1357)	2024-09-04 11:55:35 +01:00
pack.h	gowin: Himbaechel. Add ALU.	2023-08-31 08:28:09 +02:00