YRabbit 8f87918230 Gowin. Add fix for Single Port BSRAM ... Add description of BSRAM harness In some cases, Gowin IDE adds a number of LUTs and DFFs to the BSRAM. Here we are trying to add similar elements. More details with pictures: https://github.com/YosysHQ/apicula/blob/master/doc/bsram-fix.md Signed-off-by: YRabbit <rabbit@yrabbit.cyou>		2024-06-25 11:14:02 +02:00
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CMakeLists.txt	gowin: Himbaechel. Add GW1NZ-1 BSRAM.	2023-11-26 13:08:09 +01:00
constids.inc	Gowin. Add fix for Single Port BSRAM	2024-06-25 11:14:02 +02:00
cst.cc	gowin: Himbaechel. Extend clock router	2023-09-08 09:15:35 +02:00
cst.h	gowin: Himbaechel. Add constraint file processing.	2023-08-31 08:28:09 +02:00
globals.cc	gowin: Add support for DSP primitives.	2024-03-22 09:47:10 +00:00
globals.h	gowin: Himbaechel. Add a clock router.	2023-08-31 08:28:09 +02:00
gowin_arch_gen.py	Gowin. Add fix for Single Port BSRAM	2024-06-25 11:14:02 +02:00
gowin_utils.cc	Gowin. Add fix for Single Port BSRAM	2024-06-25 11:14:02 +02:00
gowin_utils.h	Gowin. Add fix for Single Port BSRAM	2024-06-25 11:14:02 +02:00
gowin.cc	Gowin. Add fix for Single Port BSRAM	2024-06-25 11:14:02 +02:00
gowin.h	Gowin. Add fix for Single Port BSRAM	2024-06-25 11:14:02 +02:00
pack.cc	Gowin. Add fix for Single Port BSRAM	2024-06-25 11:14:02 +02:00
pack.h	gowin: Himbaechel. Add ALU.	2023-08-31 08:28:09 +02:00