264 lines
9.2 KiB
C++
264 lines
9.2 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@clifford.at>
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* Copyright (C) 2018 David Shah <david@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "cells.h"
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#include "design_utils.h"
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#include "log.h"
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NEXTPNR_NAMESPACE_BEGIN
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void add_port(const Context *ctx, CellInfo *cell, std::string name,
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PortType dir)
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{
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IdString id = ctx->id(name);
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cell->ports[id] = PortInfo{id, nullptr, dir};
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}
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CellInfo *create_ice_cell(Context *ctx, IdString type, std::string name)
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{
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static int auto_idx = 0;
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CellInfo *new_cell = new CellInfo();
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if (name.empty()) {
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new_cell->name = IdString(ctx, "$nextpnr_" + type.str() + "_" +
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std::to_string(auto_idx++));
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} else {
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new_cell->name = ctx->id(name);
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}
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new_cell->type = type;
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if (type == ctx->id("ICESTORM_LC")) {
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new_cell->params[ctx->id("LUT_INIT")] = "0";
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new_cell->params[ctx->id("NEG_CLK")] = "0";
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new_cell->params[ctx->id("CARRY_ENABLE")] = "0";
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new_cell->params[ctx->id("DFF_ENABLE")] = "0";
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new_cell->params[ctx->id("SET_NORESET")] = "0";
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new_cell->params[ctx->id("ASYNC_SR")] = "0";
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add_port(ctx, new_cell, "I0", PORT_IN);
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add_port(ctx, new_cell, "I1", PORT_IN);
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add_port(ctx, new_cell, "I2", PORT_IN);
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add_port(ctx, new_cell, "I3", PORT_IN);
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add_port(ctx, new_cell, "CIN", PORT_IN);
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add_port(ctx, new_cell, "CLK", PORT_IN);
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add_port(ctx, new_cell, "CEN", PORT_IN);
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add_port(ctx, new_cell, "SR", PORT_IN);
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add_port(ctx, new_cell, "LO", PORT_OUT);
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add_port(ctx, new_cell, "O", PORT_OUT);
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add_port(ctx, new_cell, "OUT", PORT_OUT);
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} else if (type == ctx->id("SB_IO")) {
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new_cell->params[ctx->id("PIN_TYPE")] = "0";
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new_cell->params[ctx->id("PULLUP")] = "0";
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new_cell->params[ctx->id("NEG_TRIGGER")] = "0";
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new_cell->params[ctx->id("IOSTANDARD")] = "SB_LVCMOS";
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add_port(ctx, new_cell, "PACKAGE_PIN", PORT_INOUT);
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add_port(ctx, new_cell, "LATCH_INPUT_VALUE", PORT_IN);
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add_port(ctx, new_cell, "CLOCK_ENABLE", PORT_IN);
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add_port(ctx, new_cell, "INPUT_CLK", PORT_IN);
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add_port(ctx, new_cell, "OUTPUT_CLK", PORT_IN);
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add_port(ctx, new_cell, "OUTPUT_ENABLE", PORT_IN);
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add_port(ctx, new_cell, "D_OUT_0", PORT_IN);
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add_port(ctx, new_cell, "D_OUT_1", PORT_IN);
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add_port(ctx, new_cell, "D_IN_0", PORT_OUT);
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add_port(ctx, new_cell, "D_IN_1", PORT_OUT);
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} else if (type == ctx->id("ICESTORM_RAM")) {
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new_cell->params[ctx->id("NEG_CLK_W")] = "0";
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new_cell->params[ctx->id("NEG_CLK_R")] = "0";
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new_cell->params[ctx->id("WRITE_MODE")] = "0";
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new_cell->params[ctx->id("READ_MODE")] = "0";
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add_port(ctx, new_cell, "RCLK", PORT_IN);
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add_port(ctx, new_cell, "RCLKE", PORT_IN);
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add_port(ctx, new_cell, "RE", PORT_IN);
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add_port(ctx, new_cell, "WCLK", PORT_IN);
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add_port(ctx, new_cell, "WCLKE", PORT_IN);
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add_port(ctx, new_cell, "WE", PORT_IN);
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for (int i = 0; i < 16; i++) {
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add_port(ctx, new_cell, "WDATA_" + std::to_string(i), PORT_IN);
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add_port(ctx, new_cell, "MASK_" + std::to_string(i), PORT_IN);
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add_port(ctx, new_cell, "RDATA_" + std::to_string(i), PORT_OUT);
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}
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for (int i = 0; i < 11; i++) {
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add_port(ctx, new_cell, "RADDR_" + std::to_string(i), PORT_IN);
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add_port(ctx, new_cell, "WADDR_" + std::to_string(i), PORT_IN);
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}
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} else if (type == ctx->id("SB_GB")) {
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add_port(ctx, new_cell, "USER_SIGNAL_TO_GLOBAL_BUFFER", PORT_IN);
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add_port(ctx, new_cell, "GLOBAL_BUFFER_OUTPUT", PORT_OUT);
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} else {
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log_error("unable to create iCE40 cell of type %s", type.c_str());
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}
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return new_cell;
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}
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void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
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{
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lc->params["LUT_INIT"] = lut->params["LUT_INIT"];
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replace_port(lut, "I0", lc, "I0");
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replace_port(lut, "I1", lc, "I1");
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replace_port(lut, "I2", lc, "I2");
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replace_port(lut, "I3", lc, "I3");
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if (no_dff) {
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replace_port(lut, "O", lc, "O");
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lc->params["DFF_ENABLE"] = "0";
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}
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}
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void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc,
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bool pass_thru_lut)
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{
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lc->params[ctx->id("DFF_ENABLE")] = "1";
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std::string config = dff->type.str(ctx).substr(6);
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auto citer = config.begin();
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replace_port(dff, "C", lc, "CLK");
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if (citer != config.end() && *citer == 'N') {
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lc->params[ctx->id("NEG_CLK")] = "1";
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++citer;
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} else {
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lc->params[ctx->id("NEG_CLK")] = "0";
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}
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if (citer != config.end() && *citer == 'E') {
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replace_port(dff, "E", lc, "CEN");
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++citer;
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}
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if (citer != config.end()) {
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if ((config.end() - citer) >= 2) {
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char c = *(citer++);
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assert(c == 'S');
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lc->params[ctx->id("ASYNC_SR")] = "0";
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} else {
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lc->params[ctx->id("ASYNC_SR")] = "1";
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}
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if (*citer == 'S') {
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citer++;
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replace_port(dff, "S", lc, "SR");
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lc->params[ctx->id("SET_NORESET")] = "1";
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} else {
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assert(*citer == 'R');
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citer++;
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replace_port(dff, "R", lc, "SR");
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lc->params[ctx->id("SET_NORESET")] = "0";
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}
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}
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assert(citer == config.end());
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if (pass_thru_lut) {
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lc->params[ctx->id("LUT_INIT")] = "2";
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replace_port(dff, "D", lc, "I0");
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}
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replace_port(dff, "Q", lc, "O");
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}
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void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio)
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{
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if (nxio->type == ctx->id("$nextpnr_ibuf")) {
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sbio->params[ctx->id("PIN_TYPE")] = "1";
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auto pu_attr = nxio->attrs.find("PULLUP");
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if (pu_attr != nxio->attrs.end())
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sbio->params[ctx->id("PULLUP")] = pu_attr->second;
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replace_port(nxio, "O", sbio, "D_IN_0");
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} else if (nxio->type == ctx->id("$nextpnr_obuf")) {
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sbio->params[ctx->id("PIN_TYPE")] = "25";
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replace_port(nxio, "I", sbio, "D_OUT_0");
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} else if (nxio->type == ctx->id("$nextpnr_iobuf")) {
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// N.B. tristate will be dealt with below
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sbio->params[ctx->id("PIN_TYPE")] = "25";
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replace_port(nxio, "I", sbio, "D_OUT_0");
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replace_port(nxio, "O", sbio, "D_IN_0");
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} else {
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assert(false);
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}
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NetInfo *donet = sbio->ports.at(ctx->id("D_OUT_0")).net;
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CellInfo *tbuf =
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net_driven_by(ctx, donet,
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[](const Context *ctx, const CellInfo *cell) {
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return cell->type == ctx->id("$_TBUF_");
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},
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"Y");
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if (tbuf) {
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sbio->params[ctx->id("PIN_TYPE")] = "41";
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replace_port(tbuf, "A", sbio, "D_OUT_0");
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replace_port(tbuf, "E", sbio, "OUTPUT_ENABLE");
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ctx->nets.erase(donet->name);
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if (!donet->users.empty())
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log_error(
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"unsupported tristate IO pattern for IO buffer '%s', "
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"instantiate SB_IO manually to ensure correct behaviour\n",
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nxio->name.c_str(ctx));
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ctx->cells.erase(tbuf->name);
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}
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}
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bool is_clock_port(const Context *ctx, const PortRef &port)
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{
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if (port.cell == nullptr)
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return false;
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if (is_ff(ctx, port.cell))
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return port.port == ctx->id("C");
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if (port.cell->type == ctx->id("ICESTORM_LC"))
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return port.port == ctx->id("CLK");
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if (is_ram(ctx, port.cell) || port.cell->type == ctx->id("ICESTORM_RAM"))
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return port.port == ctx->id("RCLK") || port.port == ctx->id("WCLK");
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return false;
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}
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bool is_reset_port(const Context *ctx, const PortRef &port)
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{
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if (port.cell == nullptr)
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return false;
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if (is_ff(ctx, port.cell))
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return port.port == ctx->id("R") || port.port == ctx->id("S");
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if (port.cell->type == ctx->id("ICESTORM_LC"))
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return port.port == ctx->id("SR");
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return false;
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}
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bool is_enable_port(const Context *ctx, const PortRef &port)
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{
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if (port.cell == nullptr)
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return false;
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if (is_ff(ctx, port.cell))
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return port.port == ctx->id("E");
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if (port.cell->type == ctx->id("ICESTORM_LC"))
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return port.port == ctx->id("CEN");
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return false;
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}
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bool is_global_net(const Context *ctx, const NetInfo *net)
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{
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return bool(
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net_driven_by(ctx, net, is_gbuf, ctx->id("GLOBAL_BUFFER_OUTPUT")));
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}
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NEXTPNR_NAMESPACE_END
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