90d4863dd4
The following primitives are implemented for the GW1NZ-1 chip: * pROM - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32). * pROMX9 - read only memory - (bitwidth: 9, 18, 36). * SDPB - semidual port - (bitwidth: 1, 2, 4, 8, 16, 32). * SDPX9B - semidual port - (bitwidth: 9, 18, 36). * DPB - dual port - (bitwidth: 16). * DPX9B - dual port - (bitwidth: 18). * SP - single port - (bitwidth: 1, 2, 4, 8, 16, 32). * SPX9 - single port - (bitwidth: 9, 18, 36). Also: - The creation of databases for GW1NS-2 has been removed - this was not planned to be supported in Himbaechel from the very beginning and even examples were not created in apicula for this chip due to the lack of boards with it on sale. - It is temporarily prohibited to connect DFFs and LUTs into clusters because for some reason this prevents the creation of images on lower chips (placer cannot find the placement), although without these clusters the images are quite working. Requires further research. - Added creation of ALU with mode 0 - addition. Such an element is not generated by Yosys, but it is a favorite vendor element and its support here greatly simplifies the compilation of vendor netlists. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
112 lines
3.3 KiB
C++
112 lines
3.3 KiB
C++
#ifndef GOWIN_H
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#define GOWIN_H
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#include "nextpnr.h"
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NEXTPNR_NAMESPACE_BEGIN
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namespace {
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// Return true if a cell is a LUT
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inline bool type_is_lut(IdString cell_type) { return cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4); }
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inline bool is_lut(const CellInfo *cell) { return type_is_lut(cell->type); }
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// Return true if a cell is a DFF
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inline bool type_is_dff(IdString cell_type)
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{
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return cell_type.in(id_DFF, id_DFFE, id_DFFN, id_DFFNE, id_DFFS, id_DFFSE, id_DFFNS, id_DFFNSE, id_DFFR, id_DFFRE,
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id_DFFNR, id_DFFNRE, id_DFFP, id_DFFPE, id_DFFNP, id_DFFNPE, id_DFFC, id_DFFCE, id_DFFNC,
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id_DFFNCE);
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}
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inline bool is_dff(const CellInfo *cell) { return type_is_dff(cell->type); }
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// Return true if a cell is a ALU
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inline bool type_is_alu(IdString cell_type) { return cell_type == id_ALU; }
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inline bool is_alu(const CellInfo *cell) { return type_is_alu(cell->type); }
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inline bool type_is_diffio(IdString cell_type)
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{
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return cell_type.in(id_ELVDS_IOBUF, id_ELVDS_IBUF, id_ELVDS_TBUF, id_ELVDS_OBUF, id_TLVDS_IOBUF, id_TLVDS_IBUF,
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id_TLVDS_TBUF, id_TLVDS_OBUF);
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}
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inline bool is_diffio(const CellInfo *cell) { return type_is_diffio(cell->type); }
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inline bool type_is_iologic(IdString cell_type)
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{
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return cell_type.in(id_ODDR, id_ODDRC, id_OSER4, id_OSER8, id_OSER10, id_OVIDEO, id_IDDR, id_IDDRC, id_IDES4,
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id_IDES8, id_IDES10, id_IVIDEO);
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}
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inline bool is_iologic(const CellInfo *cell) { return type_is_iologic(cell->type); }
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// Return true if a cell is a SSRAM
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inline bool type_is_ssram(IdString cell_type) { return cell_type.in(id_RAM16SDP1, id_RAM16SDP2, id_RAM16SDP4); }
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inline bool is_ssram(const CellInfo *cell) { return type_is_ssram(cell->type); }
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// Return true if a cell is a SSRAM
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inline bool type_is_bsram(IdString cell_type)
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{
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return cell_type.in(id_SP, id_SPX9, id_pROM, id_pROMX9, id_ROM, id_SDP, id_SDPB, id_SDPX9B, id_DP, id_DPB,
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id_DPX9B);
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}
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inline bool is_bsram(const CellInfo *cell) { return type_is_bsram(cell->type); }
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// ==========================================
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// extra data in the chip db
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// ==========================================
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NPNR_PACKED_STRUCT(struct Tile_extra_data_POD {
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int32_t class_id;
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int16_t io16_x_off;
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int16_t io16_y_off;
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});
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NPNR_PACKED_STRUCT(struct Bottom_io_cnd_POD {
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int32_t wire_a_net;
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int32_t wire_b_net;
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});
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NPNR_PACKED_STRUCT(struct Bottom_io_POD {
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// simple OBUF
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static constexpr int8_t NORMAL = 0;
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// DDR
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static constexpr int8_t DDR = 1;
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RelSlice<Bottom_io_cnd_POD> conditions;
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});
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NPNR_PACKED_STRUCT(struct Extra_chip_data_POD {
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Bottom_io_POD bottom_io;
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RelSlice<IdString> diff_io_types;
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});
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} // namespace
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// Bels Z ranges. It is desirable that these numbers be synchronized with the chipdb generator
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namespace BelZ {
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enum
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{
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LUT0_Z = 0,
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LUT7_Z = 14,
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MUX20_Z = 16,
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MUX21_Z = 18,
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MUX23_Z = 22,
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MUX27_Z = 29,
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ALU0_Z = 30, // :35, 6 ALU
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RAMW_Z = 36, // RAM16SDP4
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IOBA_Z = 50,
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IOBB_Z = 51, // +IOBC...IOBL
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IOLOGICA_Z = 70,
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IDES16_Z = 72,
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OSER16_Z = 73,
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BUFG_Z = 74, // : 81 reserve just in case
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BSRAM_Z = 100,
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OSC_Z = 274,
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PLL_Z = 275,
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GSR_Z = 276,
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VCC_Z = 277,
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VSS_Z = 278
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};
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}
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NEXTPNR_NAMESPACE_END
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#endif
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