d810aac867
* Add GroupId related calls to Himbaechel API * Example uarch using new API features * Update drawGroup to propagate only GroupId
268 lines
9.5 KiB
Python
268 lines
9.5 KiB
Python
from os import path
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import sys
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sys.path.append(path.join(path.dirname(__file__), "../.."))
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from himbaechel_dbgen.chip import *
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# Grid size including IOBs at edges
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X = 100
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Y = 100
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# LUT input count
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K = 4
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# SLICEs per tile
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N = 8
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# number of local wires
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Wl = N * (K + 1) + 16
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# 1/Fc for bel input wire pips; local wire pips and neighbour pips
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Si = 6
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Sq = 6
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Sl = 1
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dirs = [ # name, dx, dy
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("N", 0, -1),
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("NE", 1, -1),
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("E", 1, 0),
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("SE", 1, 1),
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("S", 0, 1),
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("SW", -1, 1),
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("W", -1, 0),
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("NW", -1, -1)
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]
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def create_switch_matrix(tt: TileType, inputs: list[str], outputs: list[str]):
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# FIXME: terrible routing matrix, just for a toy example...
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# constant wires
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tt.create_wire("GND", "GND", const_value="GND")
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tt.create_wire("VCC", "VCC", const_value="VCC")
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# switch wires
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for i in range(Wl):
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tt.create_wire(f"SWITCH{i}", "SWITCH")
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# neighbor wires
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for i in range(Wl):
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for d, dx, dy in dirs:
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tt.create_wire(f"{d}{i}", f"NEIGH_{d}")
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# input pips
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for i, w in enumerate(inputs):
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for j in range((i % Si), Wl, Si):
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tt.create_pip(f"SWITCH{j}", w, timing_class="SWINPUT")
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# output pips
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for i, w in enumerate(outputs):
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for j in range((i % Sq), Wl, Sq):
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tt.create_pip(w, f"SWITCH{j}", timing_class="SWINPUT")
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# constant pips
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for i in range(Wl):
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tt.create_pip("GND", f"SWITCH{i}")
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tt.create_pip("VCC", f"SWITCH{i}")
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# neighbour local pips
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for i in range(Wl):
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for j, (d, dx, dy) in enumerate(dirs):
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tt.create_pip(f"{d}{(i + j) % Wl}", f"SWITCH{i}", timing_class="SWNEIGH")
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# clock "ladder"
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if not tt.has_wire("CLK"):
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tt.create_wire(f"CLK", "TILE_CLK")
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tt.create_wire(f"CLK_PREV", "CLK_ROUTE")
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tt.create_pip(f"CLK_PREV", f"CLK")
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tt.create_group("SWITCHBOX", "SWITCHBOX")
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def create_logic_tiletype(chip: Chip):
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tt = chip.create_tile_type("LOGIC")
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# setup wires
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inputs = []
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outputs = []
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for i in range(N):
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for j in range(K):
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inputs.append(f"L{i}_I{j}")
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tt.create_wire(f"L{i}_I{j}", "LUT_INPUT")
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tt.create_wire(f"L{i}_D", "FF_DATA")
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tt.create_wire(f"L{i}_O", "LUT_OUT")
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tt.create_wire(f"L{i}_Q", "FF_OUT")
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outputs += [f"L{i}_O", f"L{i}_Q"]
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tt.create_wire(f"CLK", "TILE_CLK")
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# create logic cells
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for i in range(N):
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# LUT
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lut = tt.create_bel(f"L{i}_LUT", "LUT4", z=(i*2 + 0))
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for j in range(K):
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tt.add_bel_pin(lut, f"I[{j}]", f"L{i}_I{j}", PinType.INPUT)
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tt.add_bel_pin(lut, "F", f"L{i}_O", PinType.OUTPUT)
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# FF data can come from LUT output or LUT I3
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tt.create_pip(f"L{i}_O", f"L{i}_D")
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tt.create_pip(f"L{i}_I{K-1}", f"L{i}_D")
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# FF
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ff = tt.create_bel(f"L{i}_FF", "DFF", z=(i*2 + 1))
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tt.add_bel_pin(ff, "D", f"L{i}_D", PinType.INPUT)
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tt.add_bel_pin(ff, "CLK", "CLK", PinType.INPUT)
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tt.add_bel_pin(ff, "Q", f"L{i}_Q", PinType.OUTPUT)
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create_switch_matrix(tt, inputs, outputs)
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return tt
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N_io = 2
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def create_io_tiletype(chip: Chip):
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tt = chip.create_tile_type("IO")
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# setup wires
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inputs = []
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outputs = []
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for i in range(N_io):
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tt.create_wire(f"IO{i}_T", "IO_T")
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tt.create_wire(f"IO{i}_I", "IO_I")
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tt.create_wire(f"IO{i}_O", "IO_O")
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tt.create_wire(f"IO{i}_PAD", "IO_PAD")
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inputs += [f"IO{i}_T", f"IO{i}_I"]
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outputs += [f"IO{i}_O", ]
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tt.create_wire(f"CLK", "TILE_CLK")
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for i in range(N_io):
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io = tt.create_bel(f"IO{i}", "IOB", z=i)
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tt.add_bel_pin(io, "I", f"IO{i}_I", PinType.INPUT)
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tt.add_bel_pin(io, "T", f"IO{i}_T", PinType.INPUT)
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tt.add_bel_pin(io, "O", f"IO{i}_O", PinType.OUTPUT)
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tt.add_bel_pin(io, "PAD", f"IO{i}_PAD", PinType.INOUT)
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# Actually used in top left IO only
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tt.create_wire("GCLK_OUT", "GCLK")
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tt.create_pip("IO0_O", "GCLK_OUT")
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create_switch_matrix(tt, inputs, outputs)
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return tt
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def create_bram_tiletype(chip: Chip):
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Aw = 9
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Dw = 16
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tt = chip.create_tile_type("BRAM")
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inputs = [f"RAM_WA{i}" for i in range(Aw)]
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inputs += [f"RAM_RA{i}" for i in range(Aw)]
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inputs += [f"RAM_WE{i}" for i in range(Dw // 8)]
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inputs += [f"RAM_DI{i}" for i in range(Dw)]
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outputs = [f"RAM_DO{i}" for i in range(Dw)]
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for w in inputs:
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tt.create_wire(w, "RAM_IN")
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for w in outputs:
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tt.create_wire(w, "RAM_OUT")
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tt.create_wire(f"CLK", "TILE_CLK")
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ram = tt.create_bel(f"RAM", F"BRAM_{2**Aw}X{Dw}", z=0)
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tt.add_bel_pin(ram, "CLK", f"CLK", PinType.INPUT)
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for i in range(Aw):
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tt.add_bel_pin(ram, f"WA[{i}]", f"RAM_WA{i}", PinType.INPUT)
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tt.add_bel_pin(ram, f"RA[{i}]", f"RAM_RA{i}", PinType.INPUT)
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for i in range(Dw//8):
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tt.add_bel_pin(ram, f"WE[{i}]", f"RAM_WE{i}", PinType.INPUT)
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for i in range(Dw):
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tt.add_bel_pin(ram, f"DI[{i}]", f"RAM_DI{i}", PinType.INPUT)
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tt.add_bel_pin(ram, f"DO[{i}]", f"RAM_DO{i}", PinType.OUTPUT)
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create_switch_matrix(tt, inputs, outputs)
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return tt
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def create_corner_tiletype(ch):
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tt = ch.create_tile_type("NULL")
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tt.create_wire(f"CLK", "TILE_CLK")
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tt.create_wire(f"CLK_PREV", "CLK_ROUTE")
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tt.create_pip(f"CLK_PREV", f"CLK")
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tt.create_wire(f"GND", "GND", const_value="GND")
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tt.create_wire(f"VCC", "VCC", const_value="VCC")
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gnd = tt.create_bel(f"GND_DRV", f"GND_DRV", z=0)
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tt.add_bel_pin(gnd, "GND", "GND", PinType.OUTPUT)
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vcc = tt.create_bel(f"VCC_DRV", f"VCC_DRV", z=1)
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tt.add_bel_pin(vcc, "VCC", "VCC", PinType.OUTPUT)
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return tt
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def is_corner(x, y):
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return ((x == 0) or (x == (X-1))) and ((y == 0) or (y == (Y-1)))
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def create_nodes(ch):
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for y in range(Y):
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#print(f"generating nodes for row {y}")
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for x in range(X):
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if not is_corner(x, y):
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# connect up actual neighbours
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local_nodes = [[NodeWire(x, y, f"SWITCH{i}")] for i in range(Wl)]
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for d, dx, dy in dirs:
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x1 = x - dx
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y1 = y - dy
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if x1 < 0 or x1 >= X or y1 < 0 or y1 >= Y or is_corner(x1, y1):
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continue
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for i in range(Wl):
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local_nodes[i].append(NodeWire(x1, y1, f"{d}{i}"))
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for n in local_nodes:
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ch.add_node(n)
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# connect up clock ladder (not intended to be a sensible clock structure)
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if y != 1: # special case where the node has 3 wires
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if y == 0:
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if x == 0:
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# clock source: IO
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clk_node = [NodeWire(1, 0, "GCLK_OUT")]
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else:
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# clock source: left
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clk_node = [NodeWire(x-1, y, "CLK")]
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else:
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# clock source: above
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clk_node = [NodeWire(x, y-1, "CLK")]
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clk_node.append(NodeWire(x, y, "CLK_PREV"))
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if y == 0:
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clk_node.append(NodeWire(x, y+1, "CLK_PREV"))
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ch.add_node(clk_node)
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def set_timings(ch):
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speed = "DEFAULT"
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tmg = ch.set_speed_grades([speed])
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# --- Routing Delays ---
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# Notes: A simpler timing model could just use intrinsic delay and ignore R and Cs.
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# R and C values don't have to be physically realistic, just in agreement with themselves to provide
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# a meaningful scaling of delay with fanout. Units are subject to change.
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tmg.set_pip_class(grade=speed, name="SWINPUT",
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delay=TimingValue(80), # 80ps intrinstic delay
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in_cap=TimingValue(5000), # 5pF
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out_res=TimingValue(1000), # 1ohm
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)
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tmg.set_pip_class(grade=speed, name="SWOUTPUT",
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delay=TimingValue(100), # 100ps intrinstic delay
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in_cap=TimingValue(5000), # 5pF
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out_res=TimingValue(800), # 0.8ohm
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)
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tmg.set_pip_class(grade=speed, name="SWNEIGH",
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delay=TimingValue(120), # 120ps intrinstic delay
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in_cap=TimingValue(7000), # 7pF
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out_res=TimingValue(1200), # 1.2ohm
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)
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# TODO: also support node/wire delays and add an example of them
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# --- Cell delays ---
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lut = ch.timing.add_cell_variant(speed, "LUT4")
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for j in range(K):
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lut.add_comb_arc(f"I[{j}]", "F", TimingValue(150 + j * 15))
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dff = ch.timing.add_cell_variant(speed, "DFF")
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dff.add_setup_hold("CLK", "D", ClockEdge.RISING, TimingValue(150), TimingValue(25))
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dff.add_clock_out("CLK", "Q", ClockEdge.RISING, TimingValue(200))
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def main():
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ch = Chip("example", "EX1", X, Y)
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# Init constant ids
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ch.strs.read_constids(path.join(path.dirname(__file__), "constids.inc"))
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ch.read_gfxids(path.join(path.dirname(__file__), "gfxids.inc"))
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logic = create_logic_tiletype(ch)
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io = create_io_tiletype(ch)
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bram = create_bram_tiletype(ch)
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null = create_corner_tiletype(ch)
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# Setup tile grid
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for x in range(X):
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for y in range(Y):
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if x == 0 or x == X-1: # left/right side IO
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if y == 0 or y == Y-1: # corner
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ch.set_tile_type(x, y, "NULL")
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else:
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ch.set_tile_type(x, y, "IO")
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elif y == 0 or y == Y-1: # top/bottom side IO
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ch.set_tile_type(x, y, "IO")
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elif (y % 15) == 7: # BRAM
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ch.set_tile_type(x, y, "BRAM")
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else:
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ch.set_tile_type(x, y, "LOGIC")
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# Create nodes between tiles
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create_nodes(ch)
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set_timings(ch)
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ch.write_bba(sys.argv[1])
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if __name__ == '__main__':
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main()
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