130 lines
3.9 KiB
C++
130 lines
3.9 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Claire Xenia Wolf <claire@yosyshq.com>
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* Copyright (C) 2021 Symbiflow Authors
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef FPGA_INTERCHANGE_ARCHDEFS_H
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#define FPGA_INTERCHANGE_ARCHDEFS_H
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#include <cstdint>
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#include "hashlib.h"
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#include "luts.h"
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#include "nextpnr_namespaces.h"
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NEXTPNR_NAMESPACE_BEGIN
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typedef int delay_t;
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// -----------------------------------------------------------------------
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struct BelId
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{
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// Tile that contains this BEL.
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int32_t tile = -1;
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// Index into tile type BEL array.
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// BEL indicies are the same for all tiles of the same type.
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int32_t index = -1;
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bool operator==(const BelId &other) const { return tile == other.tile && index == other.index; }
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bool operator!=(const BelId &other) const { return tile != other.tile || index != other.index; }
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bool operator<(const BelId &other) const
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{
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return tile < other.tile || (tile == other.tile && index < other.index);
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}
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unsigned int hash() const { return mkhash(tile, index); }
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};
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struct WireId
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{
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// Tile that contains this wire.
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int32_t tile = -1;
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int32_t index = -1;
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bool operator==(const WireId &other) const { return tile == other.tile && index == other.index; }
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bool operator!=(const WireId &other) const { return tile != other.tile || index != other.index; }
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bool operator<(const WireId &other) const
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{
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return tile < other.tile || (tile == other.tile && index < other.index);
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}
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unsigned int hash() const { return mkhash(tile, index); }
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};
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struct PipId
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{
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int32_t tile = -1;
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int32_t index = -1;
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bool operator==(const PipId &other) const { return tile == other.tile && index == other.index; }
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bool operator!=(const PipId &other) const { return tile != other.tile || index != other.index; }
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bool operator<(const PipId &other) const
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{
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return tile < other.tile || (tile == other.tile && index < other.index);
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}
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unsigned int hash() const { return mkhash(tile, index); }
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};
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struct GroupId
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{
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bool operator==(const GroupId &other) const { return true; }
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bool operator!=(const GroupId &other) const { return false; }
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unsigned int hash() const { return 0; }
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};
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struct DecalId
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{
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bool operator==(const DecalId &other) const { return true; }
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bool operator!=(const DecalId &other) const { return false; }
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unsigned int hash() const { return 0; }
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};
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struct BelBucketId
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{
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IdString name;
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bool operator==(const BelBucketId &other) const { return (name == other.name); }
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bool operator!=(const BelBucketId &other) const { return (name != other.name); }
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bool operator<(const BelBucketId &other) const { return name < other.name; }
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unsigned int hash() const { return name.hash(); }
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};
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typedef IdString ClusterId;
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struct SiteExpansionLoop;
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struct ArchNetInfo
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{
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virtual ~ArchNetInfo();
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SiteExpansionLoop *loop = nullptr;
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};
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struct ArchCellInfo
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{
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int32_t cell_mapping = -1;
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dict<IdString, std::vector<IdString>> cell_bel_pins;
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dict<IdString, std::vector<IdString>> masked_cell_bel_pins;
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pool<IdString> const_ports;
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IdString macro_parent = IdString();
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LutCell lut_cell;
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};
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NEXTPNR_NAMESPACE_END
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#endif /* FPGA_INTERCHANGE_ARCHDEFS_H */
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