825 lines
30 KiB
C++
825 lines
30 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2021 Symbiflow Authors
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*
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "log.h"
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#include "nextpnr.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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// All legal routes involved at most 2 sites, the source site and the sink
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// site. The source site and sink sites may be the same, but that is not
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// dedicated routing, that is intra site routing.
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//
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// Dedicated routing must leave the sink site, traverse some routing and
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// terminate at another site. Routing that "flys" over a site is expressed as
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// a psuedo-pip connected the relevant site pin wires, rather than traversing
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// the site.
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enum WireNodeState
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{
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IN_SINK_SITE = 0,
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IN_ROUTING = 1,
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IN_SOURCE_SITE = 2
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};
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struct WireNode
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{
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WireId wire;
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WireNodeState state;
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int depth;
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};
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// Maximum depth that a dedicate interconnect is considered.
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//
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// Routing networks with depth <= kMaxDepth is considers a dedicated
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// interconnect.
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constexpr int kMaxDepth = 20;
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void DedicatedInterconnect::init(const Context *ctx)
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{
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this->ctx = ctx;
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if (ctx->debug) {
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log_info("Finding dedicated interconnect!\n");
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}
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find_dedicated_interconnect();
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if (ctx->debug) {
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print_dedicated_interconnect();
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}
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}
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bool DedicatedInterconnect::check_routing(BelId src_bel, IdString src_bel_pin, BelId dst_bel, IdString dst_bel_pin,
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bool site_only) const
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{
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std::vector<WireNode> nodes_to_expand;
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WireId src_wire = ctx->getBelPinWire(src_bel, src_bel_pin);
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const auto &src_wire_data = ctx->wire_info(src_wire);
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NPNR_ASSERT(src_wire_data.site != -1);
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WireId dst_wire = ctx->getBelPinWire(dst_bel, dst_bel_pin);
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if (src_wire == dst_wire) {
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return true;
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}
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const auto &dst_wire_data = ctx->wire_info(dst_wire);
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NPNR_ASSERT(dst_wire_data.site != -1);
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WireNode wire_node;
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wire_node.wire = src_wire;
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wire_node.state = IN_SOURCE_SITE;
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wire_node.depth = 0;
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nodes_to_expand.push_back(wire_node);
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while (!nodes_to_expand.empty()) {
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WireNode node_to_expand = nodes_to_expand.back();
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nodes_to_expand.pop_back();
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for (PipId pip : ctx->getPipsDownhill(node_to_expand.wire)) {
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if (ctx->is_pip_synthetic(pip)) {
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continue;
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}
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WireId wire = ctx->getPipDstWire(pip);
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if (wire == WireId()) {
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continue;
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}
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if (ctx->debug) {
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log_info(" - At wire %s via %s\n", ctx->nameOfWire(wire), ctx->nameOfPip(pip));
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}
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WireNode next_node;
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next_node.wire = wire;
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next_node.depth = node_to_expand.depth += 1;
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if (next_node.depth > kMaxDepth) {
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// Dedicated routing should reach sources by kMaxDepth (with
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// tuning).
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//
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// FIXME: Consider removing kMaxDepth and use kMaxSources?
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return false;
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}
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auto const &wire_data = ctx->wire_info(wire);
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bool expand_node = true;
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if (ctx->is_site_port(pip)) {
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if (site_only) {
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// When routing site only, don't allow site ports.
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continue;
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}
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switch (node_to_expand.state) {
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case IN_SOURCE_SITE:
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NPNR_ASSERT(wire_data.site == -1);
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next_node.state = IN_ROUTING;
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break;
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case IN_ROUTING:
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NPNR_ASSERT(wire_data.site != -1);
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if (wire.tile == src_wire.tile && wire_data.site == src_wire_data.site) {
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// Dedicated routing won't have straight loops,
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// general routing looks like that.
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#ifdef DEBUG_EXPANSION
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log_info(" - Not dedicated site routing because loop!");
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#endif
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return false;
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}
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next_node.state = IN_SINK_SITE;
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break;
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case IN_SINK_SITE:
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// Once entering a site, do not leave it again.
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// This path is not a legal route!
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expand_node = false;
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break;
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default:
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// Unreachable!!!
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NPNR_ASSERT(false);
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}
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} else {
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next_node.state = node_to_expand.state;
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}
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if (expand_node) {
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nodes_to_expand.push_back(next_node);
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} else {
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continue;
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}
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if (next_node.state == IN_SINK_SITE) {
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for (BelPin bel_pin : ctx->getWireBelPins(wire)) {
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if (bel_pin.bel == dst_bel && bel_pin.pin == dst_bel_pin) {
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if (ctx->debug) {
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log_info("Valid dedicated interconnect from %s/%s to %s/%s\n", ctx->nameOfBel(src_bel),
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src_bel_pin.c_str(ctx), ctx->nameOfBel(dst_bel), dst_bel_pin.c_str(ctx));
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}
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return true;
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}
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}
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}
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}
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}
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return false;
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}
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bool DedicatedInterconnect::is_driver_on_net_valid(BelId driver_bel, const CellInfo *cell, IdString driver_port,
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NetInfo *net) const
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{
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const auto &driver_bel_data = bel_info(ctx->chip_info, driver_bel);
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TileTypeBelPin type_bel_pin;
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type_bel_pin.tile_type = ctx->chip_info->tiles[driver_bel.tile].type;
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type_bel_pin.bel_index = driver_bel.index;
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Loc driver_loc = ctx->getBelLocation(driver_bel);
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for (IdString driver_bel_pin : ctx->getBelPinsForCellPin(cell, driver_port)) {
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type_bel_pin.bel_pin = driver_bel_pin;
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auto iter = sources.find(type_bel_pin);
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if (iter == sources.end()) {
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// This BEL pin doesn't have a dedicate interconnect.
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continue;
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}
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for (const PortRef &port_ref : net->users) {
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NPNR_ASSERT(port_ref.cell != nullptr);
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if (port_ref.cell->bel == BelId()) {
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// FIXME: This should actually return "unknown!" because the
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// sink is unplaced. Once the sink is placed, this constraint
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// can be evaluated.
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if (ctx->debug) {
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log_info("BEL %s is not valid because sink cell %s/%s is not placed\n", ctx->nameOfBel(driver_bel),
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port_ref.cell->name.c_str(ctx), port_ref.port.c_str(ctx));
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}
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return false;
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}
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BelId sink_bel = port_ref.cell->bel;
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const auto &sink_bel_data = bel_info(ctx->chip_info, sink_bel);
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Loc sink_loc = ctx->getBelLocation(port_ref.cell->bel);
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if (sink_bel.tile == driver_bel.tile && sink_bel_data.site == driver_bel_data.site) {
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// This might site local routing. See if it can be routed
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for (IdString sink_bel_pin : ctx->getBelPinsForCellPin(port_ref.cell, port_ref.port)) {
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if (!check_routing(driver_bel, driver_bel_pin, sink_bel, sink_bel_pin, /*site_only=*/true)) {
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return false;
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}
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}
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continue;
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}
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DeltaTileTypeBelPin sink_type_bel_pin;
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sink_type_bel_pin.delta_x = sink_loc.x - driver_loc.x;
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sink_type_bel_pin.delta_y = sink_loc.y - driver_loc.y;
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sink_type_bel_pin.type_bel_pin.tile_type = ctx->chip_info->tiles[sink_bel.tile].type;
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sink_type_bel_pin.type_bel_pin.bel_index = sink_bel.index;
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for (IdString sink_bel_pin : ctx->getBelPinsForCellPin(port_ref.cell, port_ref.port)) {
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sink_type_bel_pin.type_bel_pin.bel_pin = sink_bel_pin;
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// Do fast routing check to see if the pair of driver and sink
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// every are valid.
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if (iter->second.count(sink_type_bel_pin) == 0) {
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if (ctx->debug) {
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log_info("BEL %s is not valid because pin %s cannot reach %s/%s\n", ctx->nameOfBel(driver_bel),
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driver_bel_pin.c_str(ctx), ctx->nameOfBel(sink_bel), sink_bel_pin.c_str(ctx));
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}
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return false;
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}
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// Do detailed routing check to ensure driver can reach sink.
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//
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// FIXME: This might be too slow, but it handles a case on
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// SLICEL.COUT -> SLICEL.CIN has delta_y = {1, 2}, but the
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// delta_y=2 case is rare.
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if (!check_routing(driver_bel, driver_bel_pin, sink_bel, sink_bel_pin, /*site_only=*/false)) {
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if (ctx->debug) {
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log_info("BEL %s is not valid because pin %s cannot be reach %s/%s (via detailed check)\n",
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ctx->nameOfBel(driver_bel), driver_bel_pin.c_str(ctx), ctx->nameOfBel(sink_bel),
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sink_bel_pin.c_str(ctx));
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}
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return false;
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}
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}
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}
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}
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return true;
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}
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bool DedicatedInterconnect::is_sink_on_net_valid(BelId bel, const CellInfo *cell, IdString port_name,
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NetInfo *net) const
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{
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const auto &bel_data = bel_info(ctx->chip_info, bel);
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Loc bel_loc = ctx->getBelLocation(bel);
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BelId driver_bel = net->driver.cell->bel;
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for (IdString bel_pin : ctx->getBelPinsForCellPin(cell, port_name)) {
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TileTypeBelPin type_bel_pin;
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type_bel_pin.tile_type = ctx->chip_info->tiles[bel.tile].type;
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type_bel_pin.bel_index = bel.index;
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type_bel_pin.bel_pin = bel_pin;
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auto iter = sinks.find(type_bel_pin);
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if (iter == sinks.end()) {
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// This BEL pin doesn't have a dedicate interconnect.
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continue;
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}
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if (driver_bel == BelId()) {
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// FIXME: This should actually return "unknown!" because the
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// driver is unplaced. Once the driver is placed, this constraint
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// can be evaluated.
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if (ctx->debug) {
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log_info("BEL %s is not valid because driver cell %s/%s is not placed\n", ctx->nameOfBel(bel),
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net->driver.cell->name.c_str(ctx), net->driver.port.c_str(ctx));
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}
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return false;
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}
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const auto &driver_bel_data = bel_info(ctx->chip_info, driver_bel);
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if (bel.tile == driver_bel.tile && bel_data.site == driver_bel_data.site) {
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// This is a site local routing, even though this is a sink
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// with a dedicated interconnect.
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continue;
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}
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Loc driver_loc = ctx->getBelLocation(driver_bel);
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DeltaTileTypeBelPin driver_type_bel_pin;
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driver_type_bel_pin.delta_x = driver_loc.x - bel_loc.x;
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driver_type_bel_pin.delta_y = driver_loc.y - bel_loc.y;
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driver_type_bel_pin.type_bel_pin.tile_type = ctx->chip_info->tiles[driver_bel.tile].type;
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driver_type_bel_pin.type_bel_pin.bel_index = driver_bel.index;
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driver_type_bel_pin.type_bel_pin.bel_pin =
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get_only_value(ctx->getBelPinsForCellPin(net->driver.cell, net->driver.port));
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// Do fast routing check to see if the pair of driver and sink
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// every are valid.
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if (iter->second.count(driver_type_bel_pin) == 0) {
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if (ctx->debug) {
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log_info("BEL %s is not valid because pin %s cannot be driven by %s/%s\n", ctx->nameOfBel(bel),
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bel_pin.c_str(ctx), ctx->nameOfBel(driver_bel),
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driver_type_bel_pin.type_bel_pin.bel_pin.c_str(ctx));
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}
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return false;
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}
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// Do detailed routing check to ensure driver can reach sink.
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//
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// FIXME: This might be too slow, but it handles a case on
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// SLICEL.COUT -> SLICEL.CIN has delta_y = {1, 2}, but the
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// delta_y=2 case is rare.
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if (!check_routing(driver_bel, driver_type_bel_pin.type_bel_pin.bel_pin, bel, bel_pin, /*site_only=*/false)) {
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if (ctx->debug) {
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log_info("BEL %s is not valid because pin %s cannot be driven by %s/%s (via detailed check)\n",
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ctx->nameOfBel(bel), bel_pin.c_str(ctx), ctx->nameOfBel(driver_bel),
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driver_type_bel_pin.type_bel_pin.bel_pin.c_str(ctx));
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}
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return false;
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}
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}
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return true;
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}
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bool DedicatedInterconnect::isBelLocationValid(BelId bel, const CellInfo *cell) const
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{
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NPNR_ASSERT(bel != BelId());
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for (const auto &port_pair : cell->ports) {
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IdString port_name = port_pair.first;
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NetInfo *net = port_pair.second.net;
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if (net == nullptr || net->driver.cell == nullptr) {
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continue;
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}
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// Only check sink BELs.
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if (net->driver.cell == cell && net->driver.port == port_name) {
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if (!is_driver_on_net_valid(bel, cell, port_name, net)) {
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return false;
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}
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} else {
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if (!is_sink_on_net_valid(bel, cell, port_name, net)) {
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return false;
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}
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}
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}
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return true;
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}
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void DedicatedInterconnect::explain_bel_status(BelId bel, const CellInfo *cell) const
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{
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NPNR_ASSERT(bel != BelId());
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for (const auto &port_pair : cell->ports) {
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IdString port_name = port_pair.first;
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NetInfo *net = port_pair.second.net;
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if (net == nullptr) {
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continue;
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}
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// This net doesn't have a driver, probably not valid?
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NPNR_ASSERT(net->driver.cell != nullptr);
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// Only check sink BELs.
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if (net->driver.cell == cell && net->driver.port == port_name) {
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if (!is_driver_on_net_valid(bel, cell, port_name, net)) {
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log_info("Driver %s/%s is not valid on net '%s'", cell->name.c_str(ctx), port_name.c_str(ctx),
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net->name.c_str(ctx));
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}
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} else {
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if (!is_sink_on_net_valid(bel, cell, port_name, net)) {
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log_info("Sink %s/%s is not valid on net '%s'", cell->name.c_str(ctx), port_name.c_str(ctx),
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net->name.c_str(ctx));
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}
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}
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}
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}
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void DedicatedInterconnect::print_dedicated_interconnect() const
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{
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log_info("Found %zu sinks with dedicated interconnect\n", sinks.size());
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log_info("Found %zu sources with dedicated interconnect\n", sources.size());
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std::vector<TileTypeBelPin> sorted_keys;
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for (const auto &sink_to_srcs : sinks) {
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sorted_keys.push_back(sink_to_srcs.first);
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}
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for (const auto &src_to_sinks : sources) {
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sorted_keys.push_back(src_to_sinks.first);
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}
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std::sort(sorted_keys.begin(), sorted_keys.end());
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for (const auto &key : sorted_keys) {
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auto iter = sinks.find(key);
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if (iter != sinks.end()) {
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auto dst = key;
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for (const auto &src_delta : iter->second) {
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auto src = src_delta.type_bel_pin;
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auto delta_x = src_delta.delta_x;
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auto delta_y = src_delta.delta_y;
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const TileTypeInfoPOD &src_tile_type = ctx->chip_info->tile_types[src.tile_type];
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const BelInfoPOD &src_bel_info = src_tile_type.bel_data[src.bel_index];
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IdString src_site_type = IdString(src_tile_type.site_types[src_bel_info.site]);
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IdString src_bel_pin = src.bel_pin;
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const TileTypeInfoPOD &dst_tile_type = ctx->chip_info->tile_types[dst.tile_type];
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const BelInfoPOD &dst_bel_info = dst_tile_type.bel_data[dst.bel_index];
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IdString dst_site_type = IdString(dst_tile_type.site_types[dst_bel_info.site]);
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IdString dst_bel_pin = dst.bel_pin;
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log_info("%s.%s[%d]/%s/%s (%d, %d) -> %s.%s[%d]/%s/%s\n", IdString(src_tile_type.name).c_str(ctx),
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src_site_type.c_str(ctx), src_bel_info.site, IdString(src_bel_info.name).c_str(ctx),
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src_bel_pin.c_str(ctx), delta_x, delta_y, IdString(dst_tile_type.name).c_str(ctx),
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dst_site_type.c_str(ctx), dst_bel_info.site, IdString(dst_bel_info.name).c_str(ctx),
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dst_bel_pin.c_str(ctx));
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}
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} else {
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auto src = key;
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for (const auto &dst_delta : sources.at(key)) {
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auto dst = dst_delta.type_bel_pin;
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auto delta_x = dst_delta.delta_x;
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auto delta_y = dst_delta.delta_y;
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const TileTypeInfoPOD &src_tile_type = ctx->chip_info->tile_types[src.tile_type];
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const BelInfoPOD &src_bel_info = src_tile_type.bel_data[src.bel_index];
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IdString src_site_type = IdString(src_tile_type.site_types[src_bel_info.site]);
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IdString src_bel_pin = src.bel_pin;
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const TileTypeInfoPOD &dst_tile_type = ctx->chip_info->tile_types[dst.tile_type];
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const BelInfoPOD &dst_bel_info = dst_tile_type.bel_data[dst.bel_index];
|
|
IdString dst_site_type = IdString(dst_tile_type.site_types[dst_bel_info.site]);
|
|
IdString dst_bel_pin = dst.bel_pin;
|
|
|
|
log_info("%s.%s[%d]/%s/%s -> %s.%s[%d]/%s/%s (%d, %d)\n", IdString(src_tile_type.name).c_str(ctx),
|
|
src_site_type.c_str(ctx), src_bel_info.site, IdString(src_bel_info.name).c_str(ctx),
|
|
src_bel_pin.c_str(ctx), IdString(dst_tile_type.name).c_str(ctx), dst_site_type.c_str(ctx),
|
|
dst_bel_info.site, IdString(dst_bel_info.name).c_str(ctx), dst_bel_pin.c_str(ctx), delta_x,
|
|
delta_y);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void DedicatedInterconnect::find_dedicated_interconnect()
|
|
{
|
|
for (BelId bel : ctx->getBels()) {
|
|
const auto &bel_data = bel_info(ctx->chip_info, bel);
|
|
if (bel_data.category != BEL_CATEGORY_LOGIC) {
|
|
continue;
|
|
}
|
|
if (bel_data.synthetic) {
|
|
continue;
|
|
}
|
|
|
|
for (int i = 0; i < bel_data.num_bel_wires; ++i) {
|
|
if (bel_data.types[i] != PORT_IN) {
|
|
continue;
|
|
}
|
|
|
|
WireId wire;
|
|
wire.tile = bel.tile;
|
|
wire.index = bel_data.wires[i];
|
|
|
|
expand_sink_bel(bel, IdString(bel_data.ports[i]), wire);
|
|
}
|
|
}
|
|
|
|
pool<TileTypeBelPin> seen_pins;
|
|
for (auto sink_pair : sinks) {
|
|
for (auto src : sink_pair.second) {
|
|
seen_pins.emplace(src.type_bel_pin);
|
|
}
|
|
}
|
|
|
|
for (BelId bel : ctx->getBels()) {
|
|
const auto &bel_data = bel_info(ctx->chip_info, bel);
|
|
if (bel_data.category != BEL_CATEGORY_LOGIC) {
|
|
continue;
|
|
}
|
|
if (bel_data.synthetic) {
|
|
continue;
|
|
}
|
|
|
|
for (int i = 0; i < bel_data.num_bel_wires; ++i) {
|
|
if (bel_data.types[i] != PORT_OUT || bel_data.wires[i] == -1) {
|
|
continue;
|
|
}
|
|
|
|
IdString bel_pin(bel_data.ports[i]);
|
|
|
|
TileTypeBelPin type_bel_pin;
|
|
type_bel_pin.tile_type = ctx->chip_info->tiles[bel.tile].type;
|
|
type_bel_pin.bel_index = bel.index;
|
|
type_bel_pin.bel_pin = bel_pin;
|
|
|
|
// Don't visit src pins already handled in the sink expansion!
|
|
if (seen_pins.count(type_bel_pin)) {
|
|
continue;
|
|
}
|
|
|
|
WireId wire;
|
|
wire.tile = bel.tile;
|
|
wire.index = bel_data.wires[i];
|
|
|
|
expand_source_bel(bel, bel_pin, wire);
|
|
}
|
|
}
|
|
}
|
|
|
|
void DedicatedInterconnect::expand_sink_bel(BelId sink_bel, IdString sink_pin, WireId sink_wire)
|
|
{
|
|
NPNR_ASSERT(sink_bel != BelId());
|
|
#ifdef DEBUG_EXPANSION
|
|
log_info("Expanding from %s/%s\n", ctx->nameOfBel(sink_bel), pin.c_str(ctx));
|
|
#endif
|
|
|
|
std::vector<WireNode> nodes_to_expand;
|
|
|
|
const auto &sink_wire_data = ctx->wire_info(sink_wire);
|
|
NPNR_ASSERT(sink_wire_data.site != -1);
|
|
|
|
WireNode wire_node;
|
|
wire_node.wire = sink_wire;
|
|
wire_node.state = IN_SINK_SITE;
|
|
wire_node.depth = 0;
|
|
|
|
nodes_to_expand.push_back(wire_node);
|
|
|
|
Loc sink_loc = ctx->getBelLocation(sink_bel);
|
|
pool<DeltaTileTypeBelPin> srcs;
|
|
|
|
while (!nodes_to_expand.empty()) {
|
|
WireNode node_to_expand = nodes_to_expand.back();
|
|
nodes_to_expand.pop_back();
|
|
|
|
for (PipId pip : ctx->getPipsUphill(node_to_expand.wire)) {
|
|
if (ctx->is_pip_synthetic(pip)) {
|
|
continue;
|
|
}
|
|
|
|
WireId wire = ctx->getPipSrcWire(pip);
|
|
if (wire == WireId()) {
|
|
continue;
|
|
}
|
|
|
|
#ifdef DEBUG_EXPANSION
|
|
log_info(" - At wire %s via %s\n", ctx->nameOfWire(wire), ctx->nameOfPip(pip));
|
|
#endif
|
|
|
|
WireNode next_node;
|
|
next_node.wire = wire;
|
|
next_node.depth = node_to_expand.depth += 1;
|
|
|
|
if (next_node.depth > kMaxDepth) {
|
|
// Dedicated routing should reach sources by kMaxDepth (with
|
|
// tuning).
|
|
//
|
|
// FIXME: Consider removing kMaxDepth and use kMaxSources?
|
|
#ifdef DEBUG_EXPANSION
|
|
log_info(" - Exceeded max depth!\n");
|
|
#endif
|
|
return;
|
|
}
|
|
|
|
auto const &wire_data = ctx->wire_info(wire);
|
|
|
|
bool expand_node = true;
|
|
if (ctx->is_site_port(pip)) {
|
|
switch (node_to_expand.state) {
|
|
case IN_SINK_SITE:
|
|
NPNR_ASSERT(wire_data.site == -1);
|
|
next_node.state = IN_ROUTING;
|
|
break;
|
|
case IN_ROUTING:
|
|
NPNR_ASSERT(wire_data.site != -1);
|
|
if (wire.tile == sink_wire.tile && wire_data.site == sink_wire_data.site) {
|
|
// Dedicated routing won't have straight loops,
|
|
// general routing looks like that.
|
|
#ifdef DEBUG_EXPANSION
|
|
log_info(" - Not dedicated site routing because loop!");
|
|
#endif
|
|
return;
|
|
}
|
|
next_node.state = IN_SOURCE_SITE;
|
|
break;
|
|
case IN_SOURCE_SITE:
|
|
// Once entering a site, do not leave it again.
|
|
// This path is not a legal route!
|
|
expand_node = false;
|
|
break;
|
|
default:
|
|
// Unreachable!!!
|
|
NPNR_ASSERT(false);
|
|
}
|
|
} else {
|
|
next_node.state = node_to_expand.state;
|
|
}
|
|
|
|
if (expand_node) {
|
|
nodes_to_expand.push_back(next_node);
|
|
} else {
|
|
continue;
|
|
}
|
|
|
|
if (next_node.state == IN_SOURCE_SITE) {
|
|
for (BelPin bel_pin : ctx->getWireBelPins(wire)) {
|
|
BelId src_bel = bel_pin.bel;
|
|
auto const &bel_data = bel_info(ctx->chip_info, src_bel);
|
|
|
|
if (bel_data.category != BEL_CATEGORY_LOGIC) {
|
|
continue;
|
|
}
|
|
if (bel_data.synthetic) {
|
|
continue;
|
|
}
|
|
if (ctx->getBelPinType(bel_pin.bel, bel_pin.pin) != PORT_OUT) {
|
|
continue;
|
|
}
|
|
|
|
#ifdef DEBUG_EXPANSION
|
|
log_info(" - Reached %s/%s\n", ctx->nameOfBel(bel_pin.bel), bel_pin.pin.c_str(ctx));
|
|
#endif
|
|
|
|
Loc src_loc = ctx->getBelLocation(src_bel);
|
|
|
|
DeltaTileTypeBelPin delta_type_bel_pin;
|
|
delta_type_bel_pin.delta_x = src_loc.x - sink_loc.x;
|
|
delta_type_bel_pin.delta_y = src_loc.y - sink_loc.y;
|
|
delta_type_bel_pin.type_bel_pin.tile_type = ctx->chip_info->tiles[src_bel.tile].type;
|
|
delta_type_bel_pin.type_bel_pin.bel_index = src_bel.index;
|
|
delta_type_bel_pin.type_bel_pin.bel_pin = bel_pin.pin;
|
|
srcs.emplace(delta_type_bel_pin);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TileTypeBelPin type_bel_pin;
|
|
type_bel_pin.tile_type = ctx->chip_info->tiles[sink_bel.tile].type;
|
|
type_bel_pin.bel_index = sink_bel.index;
|
|
type_bel_pin.bel_pin = sink_pin;
|
|
|
|
auto result = sinks.emplace(type_bel_pin, srcs);
|
|
if (!result.second) {
|
|
// type_bel_pin was already present! Add any new sources from this
|
|
// sink type (if any);
|
|
for (auto src : srcs) {
|
|
result.first->second.emplace(src);
|
|
}
|
|
}
|
|
}
|
|
|
|
void DedicatedInterconnect::expand_source_bel(BelId src_bel, IdString src_pin, WireId src_wire)
|
|
{
|
|
NPNR_ASSERT(src_bel != BelId());
|
|
#ifdef DEBUG_EXPANSION
|
|
log_info("Expanding from %s/%s\n", ctx->nameOfBel(src_bel), src_pin.c_str(ctx));
|
|
#endif
|
|
|
|
std::vector<WireNode> nodes_to_expand;
|
|
|
|
const auto &src_wire_data = ctx->wire_info(src_wire);
|
|
NPNR_ASSERT(src_wire_data.site != -1);
|
|
|
|
WireNode wire_node;
|
|
wire_node.wire = src_wire;
|
|
wire_node.state = IN_SOURCE_SITE;
|
|
wire_node.depth = 0;
|
|
|
|
nodes_to_expand.push_back(wire_node);
|
|
|
|
Loc src_loc = ctx->getBelLocation(src_bel);
|
|
pool<DeltaTileTypeBelPin> dsts;
|
|
|
|
while (!nodes_to_expand.empty()) {
|
|
WireNode node_to_expand = nodes_to_expand.back();
|
|
nodes_to_expand.pop_back();
|
|
|
|
for (PipId pip : ctx->getPipsDownhill(node_to_expand.wire)) {
|
|
if (ctx->is_pip_synthetic(pip)) {
|
|
continue;
|
|
}
|
|
|
|
WireId wire = ctx->getPipDstWire(pip);
|
|
if (wire == WireId()) {
|
|
continue;
|
|
}
|
|
|
|
#ifdef DEBUG_EXPANSION
|
|
log_info(" - At wire %s via %s\n", ctx->nameOfWire(wire), ctx->nameOfPip(pip));
|
|
#endif
|
|
|
|
WireNode next_node;
|
|
next_node.wire = wire;
|
|
next_node.depth = node_to_expand.depth += 1;
|
|
|
|
if (next_node.depth > kMaxDepth) {
|
|
// Dedicated routing should reach sources by kMaxDepth (with
|
|
// tuning).
|
|
//
|
|
// FIXME: Consider removing kMaxDepth and use kMaxSources?
|
|
#ifdef DEBUG_EXPANSION
|
|
log_info(" - Exceeded max depth!\n");
|
|
#endif
|
|
return;
|
|
}
|
|
|
|
auto const &wire_data = ctx->wire_info(wire);
|
|
|
|
bool expand_node = true;
|
|
if (ctx->is_site_port(pip)) {
|
|
switch (node_to_expand.state) {
|
|
case IN_SOURCE_SITE:
|
|
NPNR_ASSERT(wire_data.site == -1);
|
|
next_node.state = IN_ROUTING;
|
|
break;
|
|
case IN_ROUTING:
|
|
NPNR_ASSERT(wire_data.site != -1);
|
|
if (wire.tile == src_wire.tile && wire_data.site == src_wire_data.site) {
|
|
// Dedicated routing won't have straight loops,
|
|
// general routing looks like that.
|
|
#ifdef DEBUG_EXPANSION
|
|
log_info(" - Not dedicated site routing because loop!");
|
|
#endif
|
|
return;
|
|
}
|
|
next_node.state = IN_SINK_SITE;
|
|
break;
|
|
case IN_SINK_SITE:
|
|
// Once entering a site, do not leave it again.
|
|
// This path is not a legal route!
|
|
expand_node = false;
|
|
break;
|
|
default:
|
|
// Unreachable!!!
|
|
NPNR_ASSERT(false);
|
|
}
|
|
} else {
|
|
next_node.state = node_to_expand.state;
|
|
}
|
|
|
|
if (expand_node) {
|
|
nodes_to_expand.push_back(next_node);
|
|
} else {
|
|
continue;
|
|
}
|
|
|
|
if (next_node.state == IN_SINK_SITE) {
|
|
for (BelPin bel_pin : ctx->getWireBelPins(wire)) {
|
|
BelId sink_bel = bel_pin.bel;
|
|
auto const &bel_data = bel_info(ctx->chip_info, sink_bel);
|
|
|
|
if (bel_data.category != BEL_CATEGORY_LOGIC) {
|
|
continue;
|
|
}
|
|
if (bel_data.synthetic) {
|
|
continue;
|
|
}
|
|
if (ctx->getBelPinType(bel_pin.bel, bel_pin.pin) != PORT_IN) {
|
|
continue;
|
|
}
|
|
|
|
#ifdef DEBUG_EXPANSION
|
|
log_info(" - Reached %s/%s\n", ctx->nameOfBel(bel_pin.bel), bel_pin.pin.c_str(ctx));
|
|
#endif
|
|
|
|
Loc sink_loc = ctx->getBelLocation(sink_bel);
|
|
|
|
DeltaTileTypeBelPin delta_type_bel_pin;
|
|
delta_type_bel_pin.delta_x = sink_loc.x - src_loc.x;
|
|
delta_type_bel_pin.delta_y = sink_loc.y - src_loc.y;
|
|
delta_type_bel_pin.type_bel_pin.tile_type = ctx->chip_info->tiles[sink_bel.tile].type;
|
|
delta_type_bel_pin.type_bel_pin.bel_index = sink_bel.index;
|
|
delta_type_bel_pin.type_bel_pin.bel_pin = bel_pin.pin;
|
|
dsts.emplace(delta_type_bel_pin);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
TileTypeBelPin type_bel_pin;
|
|
type_bel_pin.tile_type = ctx->chip_info->tiles[src_bel.tile].type;
|
|
type_bel_pin.bel_index = src_bel.index;
|
|
type_bel_pin.bel_pin = src_pin;
|
|
|
|
auto result = sources.emplace(type_bel_pin, dsts);
|
|
if (!result.second) {
|
|
// type_bel_pin was already present! Add any new sources from this
|
|
// sink type (if any);
|
|
for (auto dst : dsts) {
|
|
result.first->second.emplace(dst);
|
|
}
|
|
}
|
|
}
|
|
|
|
NEXTPNR_NAMESPACE_END
|