27 lines
602 B
Verilog
27 lines
602 B
Verilog
module icebreaker (
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input clki,
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input btn1,
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input btn2,
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input btn3,
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output led1,
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output led2,
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output led3,
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output led4,
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output led5
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);
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wire clk;
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SB_GB clk_gb(.USER_SIGNAL_TO_GLOBAL_BUFFER(clki), .GLOBAL_BUFFER_OUTPUT(clk));
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localparam BITS = 5;
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localparam LOG2DELAY = 22;
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reg [BITS+LOG2DELAY-1:0] counter = 0;
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reg [BITS-1:0] outcnt;
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always @(posedge clk) begin
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counter <= counter + 1;
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outcnt <= counter >> LOG2DELAY;
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end
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assign {led1, led2, led3, led4, led5} = outcnt ^ (outcnt >> 1);
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//assign {led1, led2, led3, led4, led5} = {!btn1, btn2, btn3, btn2, btn1};
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endmodule
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