87 lines
1.6 KiB
Verilog
87 lines
1.6 KiB
Verilog
module \$_DFF_P_ (input D, C, output Q);
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ICESTORM_LC #(
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.LUT_INIT(1),
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.NEG_CLK(0),
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.CARRY_ENABLE(0),
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.DFF_ENABLE(1),
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.SET_NORESET(0),
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.ASYNC_SR(0)
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) _TECHMAP_REPLACE_ (
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.I0(D),
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.CLK(C),
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.O(Q),
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.I1(),
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.I2(),
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.I3(),
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.CIN(),
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.CEN(),
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.SR(),
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.LO(),
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.COUT()
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);
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endmodule
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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input [WIDTH-1:0] A;
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output Y;
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generate
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if (WIDTH == 1) begin
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ICESTORM_LC #(
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.LUT_INIT(LUT),
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.NEG_CLK(0),
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.CARRY_ENABLE(0),
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.DFF_ENABLE(0),
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.SET_NORESET(0),
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.ASYNC_SR(0)
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) _TECHMAP_REPLACE_ (
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.I0(A[0]), .I1(), .I2(), .I3(), .O(Y),
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.CLK(), .CIN(), .CEN(), .SR(), .LO(), .COUT()
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);
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end
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if (WIDTH == 2) begin
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ICESTORM_LC #(
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.LUT_INIT(LUT),
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.NEG_CLK(0),
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.CARRY_ENABLE(0),
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.DFF_ENABLE(0),
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.SET_NORESET(0),
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.ASYNC_SR(0)
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) _TECHMAP_REPLACE_ (
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.I0(A[0]), .I1(A[1]), .I2(), .I3(), .O(Y),
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.CLK(), .CIN(), .CEN(), .SR(), .LO(), .COUT()
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);
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end
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if (WIDTH == 3) begin
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ICESTORM_LC #(
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.LUT_INIT(LUT),
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.NEG_CLK(0),
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.CARRY_ENABLE(0),
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.DFF_ENABLE(0),
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.SET_NORESET(0),
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.ASYNC_SR(0)
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) _TECHMAP_REPLACE_ (
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.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(), .O(Y),
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.CLK(), .CIN(), .CEN(), .SR(), .LO(), .COUT()
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);
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end
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if (WIDTH == 4) begin
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ICESTORM_LC #(
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.LUT_INIT(LUT),
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.NEG_CLK(0),
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.CARRY_ENABLE(0),
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.DFF_ENABLE(0),
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.SET_NORESET(0),
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.ASYNC_SR(0)
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) _TECHMAP_REPLACE_ (
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.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]), .O(Y),
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.CLK(), .CIN(), .CEN(), .SR(), .LO(), .COUT()
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);
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end
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endgenerate
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endmodule
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