284 lines
10 KiB
C++
284 lines
10 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2021-22 gatecat <gatecat@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "fasm.h"
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#include "log.h"
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#include "nextpnr.h"
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#include "util.h"
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#include <algorithm>
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#include <boost/range/adaptor/reversed.hpp>
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#include <fstream>
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#define VIADUCT_CONSTIDS "viaduct/fabulous/constids.inc"
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#include "viaduct_constids.h"
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NEXTPNR_NAMESPACE_BEGIN
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namespace {
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struct FabFasmWriter
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{
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FabFasmWriter(const Context *ctx, const FabricConfig &cfg, const std::vector<PseudoPipTags> &pip_tags,
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const std::string &filename)
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: ctx(ctx), cfg(cfg), pip_tags(pip_tags), out(filename)
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{
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if (!out)
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log_error("failed to open fasm file '%s' for writing\n", filename.c_str());
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}
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std::string format_name(IdStringList name)
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{
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std::string result;
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for (IdString entry : name) {
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if (!result.empty())
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result += ".";
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result += entry.str(ctx);
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}
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return result;
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}
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void write_pip(PipId pip)
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{
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auto &data = ctx->pip_info(pip);
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if (pip.index < int(pip_tags.size()) && pip_tags.at(pip.index).type != PseudoPipTags::NONE) {
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// pseudo PIP
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const auto &tag = pip_tags.at(pip.index);
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if (tag.type == PseudoPipTags::LUT_CONST) {
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NPNR_ASSERT(ctx->checkBelAvail(tag.bel));
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prefix = format_name(ctx->getBelName(tag.bel)) + ".";
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write_int_vector(stringf("INIT[%d:0]", (1U << cfg.clb.lut_k) - 1), 0, 1U << cfg.clb.lut_k,
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(tag.data & 0x1));
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prefix = "";
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}
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return;
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}
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if (data.type.in(id_global_clock, id_O2Q) || data.type.c_str(ctx)[0] == '$')
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return; // pseudo-pips with no underlying bitstream bits
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// write pip name but with '.' instead of '/' for separator
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out << format_name(data.name) << std::endl;
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}
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void write_routing(const NetInfo *net)
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{
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std::vector<PipId> sorted_pips;
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for (auto &w : net->wires)
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if (w.second.pip != PipId())
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sorted_pips.push_back(w.second.pip);
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std::sort(sorted_pips.begin(), sorted_pips.end());
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out << stringf("# routing for net '%s'\n", ctx->nameOf(net)) << std::endl;
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for (auto pip : sorted_pips)
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write_pip(pip);
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out << std::endl;
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}
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std::string prefix;
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// Write a FASM bitvector; optionally inverting the values in the process
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void write_vector(const std::string &name, const std::vector<bool> &value, bool invert = false)
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{
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out << prefix << name << " = " << int(value.size()) << "'b";
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for (auto bit : boost::adaptors::reverse(value))
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out << ((bit ^ invert) ? '1' : '0');
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out << std::endl;
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}
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// Write a FASM bitvector given an integer value
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void write_int_vector(const std::string &name, uint64_t value, int width, bool invert = false)
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{
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std::vector<bool> bits(width, false);
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for (int i = 0; i < width; i++)
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bits[i] = (value & (1ULL << unsigned(i))) != 0;
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write_vector(name, bits, invert);
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}
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// Write an int vector param
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void write_int_vector_param(const CellInfo *cell, const std::string &name, uint64_t defval, int width,
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bool invert = false)
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{
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uint64_t value = int_or_default(cell->params, ctx->id(name), defval);
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std::vector<bool> bits(width, false);
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for (int i = 0; i < width; i++)
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bits[i] = (value & (1ULL << i)) != 0;
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write_vector(stringf("%s[%d:0]", name.c_str(), width - 1), bits, invert);
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}
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void write_bool(const CellInfo *cell, const std::string &name)
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{
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if (bool_or_default(cell->params, ctx->id(name))) {
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out << prefix << name << std::endl;
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}
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}
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void add_feature(const std::string &name) { out << prefix << name << std::endl; }
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uint64_t depermute_lut(const CellInfo *lut)
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{
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uint64_t orig_init = 0;
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if (lut->params.count(id_INIT))
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orig_init = lut->params.at(id_INIT).as_int64();
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std::vector<std::vector<unsigned>> phys_to_log;
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phys_to_log.resize(cfg.clb.lut_k);
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for (unsigned i = 0; i < cfg.clb.lut_k; i++) {
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WireId pin_wire = ctx->getBelPinWire(lut->bel, ctx->idf("I%d", i));
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for (PipId pip : ctx->getPipsUphill(pin_wire)) {
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if (!ctx->getBoundPipNet(pip))
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continue;
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unsigned pip_data = pip_tags.at(pip.index).data;
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unsigned from_pin = (pip_data >> 4) & 0xF;
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unsigned to_pin = (pip_data) & 0xF;
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NPNR_ASSERT(to_pin == i);
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phys_to_log[from_pin].push_back(i);
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}
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}
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if (bool_or_default(lut->params, id_I0MUX, false)) // internal, hardcoded
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phys_to_log[0].push_back(0);
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for (unsigned i = 0; i < cfg.clb.lut_k; i++) {
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for (auto j : phys_to_log.at(i))
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out << stringf(" # permute phys %d log %d\n", i, j);
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}
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uint64_t permuted_init = 0;
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for (unsigned i = 0; i < (1U << cfg.clb.lut_k); i++) {
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unsigned log_idx = 0;
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for (unsigned j = 0; j < cfg.clb.lut_k; j++) {
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if ((i >> j) & 0x1) {
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for (auto log_pin : phys_to_log[j])
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log_idx |= (1 << log_pin);
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}
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}
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if ((orig_init >> log_idx) & 0x1)
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permuted_init |= (uint64_t(1U) << i);
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}
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return permuted_init;
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}
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void write_logic(const CellInfo *lc)
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{
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prefix = format_name(ctx->getBelName(lc->bel)) + ".";
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if (lc->type.in(id_FABULOUS_LC, id_FABULOUS_COMB)) {
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uint64_t init = depermute_lut(lc);
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unsigned width = 1U << cfg.clb.lut_k;
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write_int_vector(stringf("INIT[%d:0]", width - 1), init, width); // todo lut depermute and thru
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if (bool_or_default(lc->params, id_I0MUX, false))
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add_feature("IOmux"); // typo in FABulous?
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}
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if (lc->type == id_FABULOUS_LC) {
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write_bool(lc, "FF");
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}
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if (lc->type.in(id_FABULOUS_LC, id_FABULOUS_FF)) {
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write_bool(lc, "SET_NORESET");
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write_bool(lc, "NEG_CLK");
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write_bool(lc, "NEG_EN");
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write_bool(lc, "NEG_SR");
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write_bool(lc, "ASYNC_SR");
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}
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if (lc->type.in(id_FABULOUS_MUX4, id_FABULOUS_MUX8)) {
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// TODO: don't hardcode prefix
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out << prefix << "I.c0" << std::endl;
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}
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if (lc->type == id_FABULOUS_MUX8) {
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// TODO: don't hardcode prefix
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out << prefix << "I.c1" << std::endl;
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}
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}
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void write_io(const CellInfo *io)
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{
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#if 0
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prefix = format_name(ctx->getBelName(io->bel)) + ".";
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write_bool(io, "INPUT_USED");
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write_bool(io, "OUTPUT_USED");
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write_bool(io, "ENABLE_USED");
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#endif
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}
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void write_generic_cell(const CellInfo *ci)
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{
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prefix = format_name(ctx->getBelName(ci->bel)) + ".";
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for (auto ¶m : ci->params) {
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// TODO: better parameter type auto-detection
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if (param.second.is_string) {
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// enum type parameter
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out << prefix << param.first.c_str(ctx) << "." << param.second.str << std::endl;
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} else if (param.second.str.size() == 1) {
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// boolean type parameter
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if (param.second.intval != 0)
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out << prefix << param.first.c_str(ctx) << std::endl;
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} else {
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// vector type parameter
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int msb = int(param.second.str.size()) - 1;
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out << prefix << param.first.c_str(ctx) << "[" << msb << ":0] = ";
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for (auto bit : boost::adaptors::reverse(param.second.str))
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out << bit;
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out << std::endl;
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}
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}
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}
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void write_iopass(const CellInfo *ci)
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{
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Loc loc = ctx->getBelLocation(ci->bel);
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// We use 'nice' names based on function for the IOPass bels inside nextpnr
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// but in the bitstream we need to use character names
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NPNR_ASSERT(loc.z <= 26);
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prefix = stringf("X%dY%d.%c.", loc.x, loc.y, 'A' + loc.z);
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if (ci->params.count(id_I_reg)) {
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uint64_t regval = int_or_default(ci->params, id_I_reg);
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for (unsigned i = 0; i < 4; i++) {
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if (regval & (1 << i))
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out << prefix << stringf("I%d_reg", i) << std::endl;
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}
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}
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prefix = "";
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}
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void write_cell(const CellInfo *ci)
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{
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out << stringf("# config for cell '%s'\n", ctx->nameOf(ci)) << std::endl;
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if (ci->type.in(id_FABULOUS_COMB, id_FABULOUS_FF, id_FABULOUS_LC, id_FABULOUS_MUX2, id_FABULOUS_MUX4,
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id_FABULOUS_MUX8))
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write_logic(ci);
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else if (ci->type == id_IO_1_bidirectional_frame_config_pass)
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write_io(ci);
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else if (ci->type.in(id_InPass4_frame_config, id_OutPass4_frame_config))
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write_iopass(ci);
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else
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write_generic_cell(ci);
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// TODO: other cell types
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out << std::endl;
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}
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void write_fasm()
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{
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for (const auto &net : ctx->nets)
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write_routing(net.second.get());
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for (const auto &cell : ctx->cells)
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write_cell(cell.second.get());
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}
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const Context *ctx;
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const FabricConfig &cfg;
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const std::vector<PseudoPipTags> &pip_tags;
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std::ofstream out;
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};
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} // namespace
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void fabulous_write_fasm(const Context *ctx, const FabricConfig &cfg, const std::vector<PseudoPipTags> &pip_tags,
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const std::string &filename)
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{
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FabFasmWriter wr(ctx, cfg, pip_tags, filename);
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wr.write_fasm();
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}
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NEXTPNR_NAMESPACE_END
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