234 lines
9.1 KiB
C++
234 lines
9.1 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2021-22 gatecat <gatecat@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "validity_check.h"
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#include "log.h"
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#include "util.h"
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#define VIADUCT_CONSTIDS "viaduct/fabulous/constids.inc"
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#include "viaduct_constids.h"
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NEXTPNR_NAMESPACE_BEGIN
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CLBState::CLBState(const LogicConfig &cfg)
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{
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// TODO: more than one per LC if in split-SLICE mode with fracturable LUTs
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lc_comb = std::make_unique<CellInfo *[]>(cfg.lc_per_clb);
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if (cfg.split_lc) {
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ff = std::make_unique<CellInfo *[]>(cfg.lc_per_clb * cfg.ff_per_lc);
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}
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mux = std::make_unique<CellInfo *[]>(cfg.lc_per_clb);
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// TODO: mux
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}
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void CellTagger::assign_for(const Context *ctx, const FabricConfig &cfg, const CellInfo *ci)
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{
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if (int(data.size()) <= ci->flat_index)
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data.resize(ci->flat_index + 1);
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auto &t = data.at(ci->flat_index);
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// Use the same logic to handle both packed and split LC modes
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if (ci->type.in(id_FABULOUS_COMB, id_FABULOUS_LC)) {
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unsigned lut_input_count = 0;
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for (unsigned i = 0; i < cfg.clb.lut_k; i++)
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if (ci->getPort(ctx->idf("I%d", i)))
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lut_input_count = i + 1;
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t.comb.lut_inputs = SSOArray<IdString, MAX_LUTK>(lut_input_count, IdString());
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for (unsigned i = 0; i < lut_input_count; i++) {
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const NetInfo *sig = ci->getPort(ctx->idf("I%d", i));
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t.comb.lut_inputs[i] = sig ? sig->name : IdString();
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}
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t.comb.carry_used = ci->getPort(id_Ci) || ci->getPort(id_Co); // TODO
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t.comb.lut_out = ci->getPort(id_O);
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}
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if (ci->type.in(id_FABULOUS_FF, id_FABULOUS_LC)) {
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if (ci->type == id_FABULOUS_FF || bool_or_default(ci->params, id_FF)) {
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t.ff.ff_used = true;
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auto get_ctrlsig = [&](IdString name) {
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const NetInfo *sig = ci->getPort(name);
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bool invert = sig && bool_or_default(ci->params, ctx->idf("NEG_%s", name.c_str(ctx)));
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if (sig && sig->driver.cell && sig->driver.cell->type.in(id__CONST0_DRV, id__CONST1_DRV)) {
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return ControlSig(((sig->driver.cell->type == id__CONST1_DRV) ^ invert) ? id__CONST1 : id__CONST0,
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false);
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}
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return ControlSig(sig ? sig->name : id___disconnected, invert);
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};
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t.ff.clk = get_ctrlsig(id_CLK);
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t.ff.sr = get_ctrlsig(id_SR);
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t.ff.en = get_ctrlsig(id_EN);
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t.ff.async = bool_or_default(ci->params, id_ASYNC_SR);
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t.ff.latch = bool_or_default(ci->params, id_LATCH_NOFF);
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t.ff.d = ci->getPort(id_D);
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t.ff.q = ci->getPort(id_Q);
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} else {
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t.ff.ff_used = false;
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}
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}
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}
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void BlockTracker::set_bel_type(BelId bel, BelFlags::BlockType block, BelFlags::FuncType func, uint8_t index)
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{
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Loc loc = ctx->getBelLocation(bel);
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if (int(tiles.size()) <= loc.y)
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tiles.resize(loc.y + 1);
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auto &row = tiles.at(loc.y);
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if (int(row.size()) <= loc.x)
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row.resize(loc.x + 1);
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auto &tile = row.at(loc.x);
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if (block == BelFlags::BLOCK_CLB) {
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if (!tile.clb)
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tile.clb = std::make_unique<CLBState>(cfg.clb);
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}
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if (int(bel_data.size()) <= bel.index)
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bel_data.resize(bel.index + 1);
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auto &flags = bel_data.at(bel.index);
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flags.block = block;
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flags.func = func;
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flags.index = index;
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}
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void BlockTracker::update_bel(BelId bel, CellInfo *old_cell, CellInfo *new_cell)
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{
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if (bel.index >= int(bel_data.size()))
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return; // some kind of bel not being tracked
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auto flags = bel_data.at(bel.index);
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if (flags.block == BelFlags::BLOCK_OTHER)
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return; // no structures to update
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Loc loc = ctx->getBelLocation(bel);
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if (loc.y >= int(tiles.size()))
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return; // some kind of bel not being tracked
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const auto &row = tiles.at(loc.y);
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if (loc.x >= int(row.size()))
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return; // some kind of bel not being tracked
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const auto &entry = row.at(loc.x);
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if (flags.block == BelFlags::BLOCK_CLB) {
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NPNR_ASSERT(entry.clb);
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// TODO: incremental validity check updates might care about this in the future, hence keeping it in the
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// interface for now
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NPNR_UNUSED(old_cell);
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if (flags.func == BelFlags::FUNC_LC_COMB)
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entry.clb->lc_comb[flags.index] = new_cell;
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else if (flags.func == BelFlags::FUNC_FF)
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entry.clb->ff[flags.index] = new_cell;
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else if (flags.func == BelFlags::FUNC_MUX)
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entry.clb->mux[flags.index] = new_cell;
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}
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}
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bool CLBState::check_validity(const LogicConfig &cfg, const CellTagger &cell_data)
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{
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SSOArray<ControlSig, 2> used_clk(cfg.clk.routing.size()), used_sr(cfg.sr.routing.size()),
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used_en(cfg.en.routing.size());
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auto check_ctrlsig = [&](unsigned idx, ControlSig actual, const ControlSetConfig &ctrl,
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SSOArray<ControlSig, 2> &used) {
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if (ctrl.can_mask != -1) {
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// Using the per-entry control signal masking
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if (actual.net == id___disconnected || (actual.net == id__CONST0 && ctrl.can_mask == 0) ||
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(actual.net == id__CONST1 && ctrl.can_mask == 0)) {
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return true;
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}
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}
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// see if we have an already-matching signal available
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for (unsigned i = 0; i < ctrl.routing.size(); i++) {
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// doesn't route to this pin
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if (((ctrl.routing.at(i) >> unsigned(idx)) & 0x1U) == 0)
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continue;
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if (used[i] == actual)
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return true;
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}
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// see if we have a free slot available
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for (unsigned i = 0; i < ctrl.routing.size(); i++) {
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// doesn't route to this pin
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if (((ctrl.routing.at(i) >> unsigned(idx)) & 0x1U) == 0)
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continue;
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if (used[i] != ControlSig())
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continue;
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used[i] = actual;
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return true;
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}
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// no option available
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return false;
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};
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for (unsigned z = 0; z < cfg.lc_per_clb; z++) {
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// flipflop control set checking
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if (cfg.split_lc) {
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NPNR_ASSERT_FALSE("unimplemented!"); // TODO
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} else {
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NPNR_ASSERT(cfg.ff_per_lc == 1); // split-slice mode must be used for more
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const CellInfo *lc = lc_comb[z];
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if (!lc)
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continue;
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auto &lct = cell_data.get(lc);
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if (lct.ff.ff_used) {
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// check shared control signals
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if (!check_ctrlsig(z, lct.ff.clk, cfg.clk, used_clk))
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return false;
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if (cfg.en.have_signal && !check_ctrlsig(z, lct.ff.en, cfg.en, used_en))
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return false;
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if (cfg.sr.have_signal && !check_ctrlsig(z, lct.ff.sr, cfg.sr, used_sr))
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return false;
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}
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}
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}
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// don't allow mixed MUX types in the classic fabulous arch where ctrl sigs are shared
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int tile_mux_type = 0;
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for (unsigned z = 0; z < cfg.lc_per_clb; z++) {
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const CellInfo *m = mux[z];
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if (!m)
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continue;
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int this_mux = 0;
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if (m->type == id_FABULOUS_MUX2)
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this_mux = 2;
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else if (m->type == id_FABULOUS_MUX4)
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this_mux = 4;
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else if (m->type == id_FABULOUS_MUX8)
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this_mux = 8;
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else
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NPNR_ASSERT_FALSE("unknown mux type");
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if (tile_mux_type == 0)
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tile_mux_type = this_mux;
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else if (tile_mux_type != this_mux)
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return false;
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}
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// TODO: other checks...
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return true;
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}
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bool BlockTracker::check_validity(BelId bel, const FabricConfig &cfg, const CellTagger &cell_data)
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{
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if (bel.index >= int(bel_data.size()))
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return true; // some kind of bel not being tracked
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auto flags = bel_data.at(bel.index);
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if (flags.block == BelFlags::BLOCK_OTHER)
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return true; // no structures to update
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Loc loc = ctx->getBelLocation(bel);
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if (loc.y >= int(tiles.size()))
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return true; // some kind of bel not being tracked
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const auto &row = tiles.at(loc.y);
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if (loc.x >= int(row.size()))
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return true; // some kind of bel not being tracked
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const auto &entry = row.at(loc.x);
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if (flags.block == BelFlags::BLOCK_CLB) {
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return entry.clb->check_validity(cfg.clb, cell_data);
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} else {
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return true;
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}
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}
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NEXTPNR_NAMESPACE_END
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