40 lines
654 B
Verilog
40 lines
654 B
Verilog
module top(input clk, cen, rst, ina, inb, output reg outa, outb, outc, outd);
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reg temp0 = 1'b0, temp1 = 1'b0;
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always @(posedge clk)
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if (cen)
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if(rst)
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temp0 <= 1'b0;
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else
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temp0 <= ina;
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always @(negedge clk)
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if (ina)
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if(rst)
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temp1 <= 1'b1;
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else
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temp1 <= inb;
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always @(posedge clk or negedge rst)
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if(!rst)
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outa <= 1'b0;
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else
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outa <= temp0;
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always @(posedge clk)
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outb <= temp1;
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always @(negedge clk)
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outc <= temp0;
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always @(negedge clk or posedge rst)
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if (rst)
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outd <= 1'b1;
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else
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outd <= temp1;
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endmodule
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