18 lines
330 B
Tcl
18 lines
330 B
Tcl
yosys -import
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foreach src $::env(SOURCES) {
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read_verilog $src
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}
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synth_xilinx -flatten -nolutram -nowidelut -nosrl -nocarry -nodsp
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techmap -map $::env(TECHMAP)
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# opt_expr -undriven makes sure all nets are driven, if only by the $undef
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# net.
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opt_expr -undriven
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opt_clean
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setundef -zero -params
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write_json $::env(OUT_JSON)
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