18 lines
290 B
Verilog
18 lines
290 B
Verilog
module top(input clk, input rst, output [7:4] io_led);
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localparam SIZE = 32;
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reg [SIZE-1:0] counter = SIZE'b0;
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assign io_led = {counter[SIZE-1], counter[25:23]};
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always @(posedge clk)
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begin
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if(rst)
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counter <= SIZE'b0;
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else
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counter <= counter + 1;
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end
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endmodule
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