267 lines
9.0 KiB
C++
267 lines
9.0 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2020 David Shah <dave@ds0.me>
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*
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "log.h"
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#include "nextpnr.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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namespace {
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struct NexusFasmWriter
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{
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const Context *ctx;
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std::ostream &out;
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std::vector<std::string> fasm_ctx;
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void push(const std::string &x) { fasm_ctx.push_back(x); }
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void pop() { fasm_ctx.pop_back(); }
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void pop(int N)
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{
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for (int i = 0; i < N; i++)
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fasm_ctx.pop_back();
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}
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bool last_was_blank = true;
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void blank()
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{
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if (!last_was_blank)
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out << std::endl;
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last_was_blank = true;
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}
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void write_prefix()
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{
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for (auto &x : fasm_ctx)
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out << x << ".";
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last_was_blank = false;
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}
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void write_bit(const std::string &name, bool value = true)
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{
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if (value) {
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write_prefix();
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out << name << std::endl;
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}
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}
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void write_comment(const std::string &cmt) { out << "# " << cmt << std::endl; }
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void write_vector(const std::string &name, const std::vector<bool> &value, bool invert = false)
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{
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write_prefix();
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out << name << " = " << int(value.size()) << "'b";
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for (auto bit : boost::adaptors::reverse(value))
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out << ((bit ^ invert) ? '1' : '0');
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out << std::endl;
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}
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void write_int_vector(const std::string &name, uint64_t value, int width, bool invert = false)
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{
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std::vector<bool> bits(width, false);
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for (int i = 0; i < width; i++)
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bits[i] = (value & (1ULL << i)) != 0;
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write_vector(name, bits, invert);
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}
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void write_enum(const CellInfo *cell, const std::string &name, const std::string &defval = "")
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{
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auto fnd = cell->params.find(ctx->id(name));
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if (fnd == cell->params.end()) {
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if (!defval.empty())
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write_bit(stringf("%s.%s", name.c_str(), defval.c_str()));
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} else {
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write_bit(stringf("%s.%s", name.c_str(), fnd->second.c_str()));
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}
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}
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NexusFasmWriter(const Context *ctx, std::ostream &out) : ctx(ctx), out(out) {}
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std::string tile_name(int loc, const PhysicalTileInfoPOD &tile)
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{
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int r = loc / ctx->chip_info->width;
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int c = loc % ctx->chip_info->width;
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return stringf("%sR%dC%d__%s", ctx->nameOf(tile.prefix), r, c, ctx->nameOf(tile.tiletype));
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}
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const PhysicalTileInfoPOD &tile_by_type_and_loc(int loc, IdString type)
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{
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auto &ploc = ctx->chip_info->grid[loc];
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for (int i = 0; i < ploc.num_phys_tiles; i++) {
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if (ploc.phys_tiles[i].tiletype == type.index)
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return ploc.phys_tiles[i];
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}
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log_error("No tile of type %s found at location R%dC%d", ctx->nameOf(type), loc / ctx->chip_info->width,
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loc % ctx->chip_info->width);
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}
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const PhysicalTileInfoPOD &tile_at_loc(int loc)
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{
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auto &ploc = ctx->chip_info->grid[loc];
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NPNR_ASSERT(ploc.num_phys_tiles == 1);
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return ploc.phys_tiles[0];
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}
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std::string escape_name(const std::string &name)
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{
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std::string escaped;
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for (char c : name) {
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if (c == ':')
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escaped += "__";
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else
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escaped += c;
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}
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return escaped;
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}
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void push_tile(int loc, IdString tile_type) { push(tile_name(loc, tile_by_type_and_loc(loc, tile_type))); }
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void push_tile(int loc) { push(tile_name(loc, tile_at_loc(loc))); }
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void push_belname(BelId bel) { push(ctx->nameOf(ctx->bel_data(bel).name)); }
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void write_pip(PipId pip)
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{
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auto &pd = ctx->pip_data(pip);
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if (pd.flags & PIP_FIXED_CONN)
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return;
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std::string tile = tile_name(pip.tile, tile_by_type_and_loc(pip.tile, pd.tile_type));
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std::string source_wire = escape_name(ctx->pip_src_wire_name(pip).str(ctx));
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std::string dest_wire = escape_name(ctx->pip_dst_wire_name(pip).str(ctx));
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write_bit(stringf("%s.PIP.%s.%s", tile.c_str(), dest_wire.c_str(), source_wire.c_str()));
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}
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void write_net(const NetInfo *net)
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{
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write_comment(stringf("Net %s", ctx->nameOf(net)));
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std::set<PipId> sorted_pips;
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for (auto &w : net->wires)
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if (w.second.pip != PipId())
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sorted_pips.insert(w.second.pip);
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for (auto p : sorted_pips)
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write_pip(p);
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blank();
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}
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void write_comb(const CellInfo *cell)
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{
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BelId bel = cell->bel;
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int z = ctx->bel_data(bel).z;
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int k = z & 0x1;
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char slice = 'A' + (z >> 3);
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push_tile(bel.tile, id_PLC);
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push(stringf("SLICE%c", slice));
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if (cell->params.count(id_INIT))
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write_int_vector(stringf("K%d.INIT[15:0]", k), int_or_default(cell->params, id_INIT, 0), 16);
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#if 0
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if (cell->lutInfo.is_carry) {
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write_bit("MODE.CCU2");
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write_enum(cell, "INJECT", "NO");
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}
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#endif
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pop(2);
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}
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void write_ff(const CellInfo *cell)
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{
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BelId bel = cell->bel;
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int z = ctx->bel_data(bel).z;
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int k = z & 0x1;
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char slice = 'A' + (z >> 3);
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push_tile(bel.tile, id_PLC);
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push(stringf("SLICE%c", slice));
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push(stringf("REG%d", k));
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write_bit("USED.YES");
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write_enum(cell, "REGSET", "RESET");
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write_enum(cell, "LSRMODE", "LSR");
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write_enum(cell, "SEL", "DF");
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pop();
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write_enum(cell, "REGDDR");
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write_enum(cell, "SRMODE");
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write_enum(cell, "CLKMUX");
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write_enum(cell, "CEMUX");
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write_enum(cell, "LSRMUX");
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write_enum(cell, "GSR");
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pop(2);
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}
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void write_io33(const CellInfo *cell)
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{
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BelId bel = cell->bel;
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push_tile(bel.tile);
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push_belname(bel);
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const NetInfo *t = get_net_or_empty(cell, id_T);
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bool is_input = false, is_output = false;
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if (t == nullptr || t->name == ctx->id("$PACKER_VCC_NET")) {
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is_input = true;
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} else if (t->name == ctx->id("$PACKER_GND_NET")) {
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is_output = true;
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}
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const char *iodir = is_input ? "INPUT" : (is_output ? "OUTPUT" : "BIDIR");
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write_bit(stringf("BASE_TYPE.%s_%s", iodir, str_or_default(cell->attrs, id_IO_TYPE, "LVCMOS33").c_str()));
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pop(2);
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}
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void write_io18(const CellInfo *cell)
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{
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BelId bel = cell->bel;
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push_tile(bel.tile);
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push_belname(bel);
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push("SEIO18");
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const NetInfo *t = get_net_or_empty(cell, id_T);
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bool is_input = false, is_output = false;
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if (t == nullptr || t->name == ctx->id("$PACKER_VCC_NET")) {
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is_input = true;
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} else if (t->name == ctx->id("$PACKER_GND_NET")) {
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is_output = true;
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}
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const char *iodir = is_input ? "INPUT" : (is_output ? "OUTPUT" : "BIDIR");
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write_bit(stringf("BASE_TYPE.%s_%s", iodir, str_or_default(cell->attrs, id_IO_TYPE, "LVCMOS18H").c_str()));
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pop(3);
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}
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void write_osc(const CellInfo *cell)
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{
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BelId bel = cell->bel;
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push_tile(bel.tile);
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push_belname(bel);
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write_enum(cell, "HF_OSC_EN");
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write_enum(cell, "HF_FABRIC_EN");
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write_enum(cell, "HFDIV_FABRIC_EN", "ENABLED");
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write_enum(cell, "LF_FABRIC_EN");
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write_enum(cell, "LF_OUTPUT_EN");
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write_int_vector(stringf("HF_CLK_DIV[7:0]"), int_or_default(cell->params, id_HF_CLK_DIV, 0), 8);
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pop(2);
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}
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void operator()()
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{
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// Write routing
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for (auto n : sorted(ctx->nets)) {
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write_net(n.second);
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}
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// Write cell config
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for (auto c : sorted(ctx->cells)) {
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const CellInfo *ci = c.second;
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write_comment(stringf("# Cell %s", ctx->nameOf(ci)));
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if (ci->type == id_OXIDE_COMB)
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write_comb(ci);
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else if (ci->type == id_OXIDE_FF)
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write_ff(ci);
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else if (ci->type == id_SEIO33_CORE)
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write_io33(ci);
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else if (ci->type == id_SEIO18_CORE)
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write_io18(ci);
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else if (ci->type == id_OSC_CORE)
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write_osc(ci);
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blank();
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}
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}
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};
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} // namespace
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void Arch::write_fasm(std::ostream &out) const { NexusFasmWriter(getCtx(), out)(); }
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NEXTPNR_NAMESPACE_END
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