38 lines
538 B
Verilog
38 lines
538 B
Verilog
module top(
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input wire [11:8] sw,
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output wire [1:0] diff_p,
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output wire [1:0] diff_n
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);
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wire [1:0] buf_i;
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wire [1:0] buf_t;
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OBUFTDS # (
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.IOSTANDARD("DIFF_SSTL135"),
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.SLEW("FAST")
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) obuftds_0 (
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.I(buf_i[0]),
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.T(buf_t[0]),
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.O(diff_p[0]),
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.OB(diff_n[0])
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);
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OBUFTDS # (
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.IOSTANDARD("DIFF_SSTL135"),
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.SLEW("FAST")
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) obuftds_1 (
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.I(buf_i[1]),
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.T(buf_t[1]),
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.O(diff_p[1]),
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.OB(diff_n[1])
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);
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assign buf_i[0] = sw[ 8];
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assign buf_t[0] = sw[ 9];
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assign buf_i[1] = sw[10];
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assign buf_t[1] = sw[11];
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endmodule
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