687 lines
26 KiB
C++
687 lines
26 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 gatecat <gatecat@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "globals.h"
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#include <algorithm>
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#include <iomanip>
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#include <queue>
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#include "cells.h"
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#include "log.h"
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#include "nextpnr.h"
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#include "place_common.h"
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#include "util.h"
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#define fmt_str(x) (static_cast<const std::ostringstream &>(std::ostringstream() << x).str())
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NEXTPNR_NAMESPACE_BEGIN
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static std::string get_quad_name(GlobalQuadrant quad)
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{
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switch (quad) {
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case QUAD_UL:
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return "UL";
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case QUAD_UR:
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return "UR";
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case QUAD_LL:
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return "LL";
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case QUAD_LR:
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return "LR";
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}
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return "";
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}
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class Ecp5GlobalRouter
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{
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public:
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Ecp5GlobalRouter(Context *ctx) : ctx(ctx){};
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private:
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bool is_clock_port(const PortRef &user)
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{
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if (user.cell->type == id_TRELLIS_FF && user.port == id_CLK)
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return true;
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if (user.cell->type == id_TRELLIS_COMB && user.port == id_WCK)
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return true;
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if (user.cell->type == id_DCUA && (user.port == id_CH0_FF_RXI_CLK || user.port == id_CH1_FF_RXI_CLK ||
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user.port == id_CH0_FF_TXI_CLK || user.port == id_CH1_FF_TXI_CLK))
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return true;
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if ((user.cell->type == id_IOLOGIC || user.cell->type == id_SIOLOGIC) && (user.port == id_CLK))
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return true;
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return false;
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}
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bool is_logic_port(const PortRef &user)
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{
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if (user.cell->type == id_TRELLIS_FF && user.port != id_CLK)
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return true;
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if (user.cell->type == id_TRELLIS_COMB && user.port != id_WCK)
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return true;
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return false;
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}
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std::vector<NetInfo *> get_clocks()
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{
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dict<IdString, int> clockCount;
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for (auto &net : ctx->nets) {
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NetInfo *ni = net.second.get();
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if (ni->name == ctx->id("$PACKER_GND_NET") || ni->name == ctx->id("$PACKER_VCC_NET") ||
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ni->driver.cell == nullptr)
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continue;
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clockCount[ni->name] = 0;
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for (const auto &user : ni->users) {
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if (is_clock_port(user)) {
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clockCount[ni->name]++;
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if (user.cell->type == id_DCUA)
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clockCount[ni->name] += 100;
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if (user.cell->type == id_IOLOGIC || user.cell->type == id_SIOLOGIC)
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clockCount[ni->name] += 10;
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}
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}
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// log_info("clkcount %s: %d\n", ni->name.c_str(ctx),clockCount[ni->name]);
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}
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// DCCAs must always drive globals
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std::vector<NetInfo *> clocks;
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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if (ci->type == id_DCCA) {
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NetInfo *glb = ci->ports.at(id_CLKO).net;
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if (glb != nullptr) {
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clocks.push_back(glb);
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clockCount.erase(glb->name);
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}
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}
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}
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while (clocks.size() < 16) {
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auto max = std::max_element(clockCount.begin(), clockCount.end(),
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[](const decltype(clockCount)::value_type &a,
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const decltype(clockCount)::value_type &b) { return a.second < b.second; });
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if (max == clockCount.end() || max->second < 5)
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break;
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clocks.push_back(ctx->nets.at(max->first).get());
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clockCount.erase(max->first);
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}
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return clocks;
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}
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PipId find_tap_pip(WireId tile_glb)
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{
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std::string wireName = ctx->get_wire_basename(tile_glb).str(ctx);
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std::string glbName = wireName.substr(2);
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TapDirection td = ctx->global_info_at_loc(tile_glb.location).tap_dir;
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WireId tap_wire;
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Location tap_loc;
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tap_loc.x = ctx->global_info_at_loc(tile_glb.location).tap_col;
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tap_loc.y = tile_glb.location.y;
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if (td == TAP_DIR_LEFT) {
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tap_wire = ctx->get_wire_by_loc_basename(tap_loc, "L_" + glbName);
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} else {
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tap_wire = ctx->get_wire_by_loc_basename(tap_loc, "R_" + glbName);
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}
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NPNR_ASSERT(tap_wire != WireId());
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return *(ctx->getPipsUphill(tap_wire).begin());
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}
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PipId find_spine_pip(WireId tap_wire)
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{
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std::string wireName = ctx->get_wire_basename(tap_wire).str(ctx);
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Location spine_loc;
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spine_loc.x = ctx->global_info_at_loc(tap_wire.location).spine_col;
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spine_loc.y = ctx->global_info_at_loc(tap_wire.location).spine_row;
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WireId spine_wire = ctx->get_wire_by_loc_basename(spine_loc, wireName);
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return *(ctx->getPipsUphill(spine_wire).begin());
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}
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void route_logic_tile_global(NetInfo *net, int global_index, PortRef user)
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{
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WireId userWire = ctx->getBelPinWire(user.cell->bel, user.port);
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WireId globalWire;
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IdString global_name = ctx->id(fmt_str("G_HPBX" << std::setw(2) << std::setfill('0') << global_index << "00"));
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std::queue<WireId> upstream;
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dict<WireId, PipId> backtrace;
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upstream.push(userWire);
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bool already_routed = false;
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WireId next;
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// Search back from the pin until we reach the global network
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while (true) {
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next = upstream.front();
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upstream.pop();
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if (ctx->getBoundWireNet(next) == net) {
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already_routed = true;
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globalWire = next;
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break;
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}
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if (ctx->get_wire_basename(next) == global_name) {
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globalWire = next;
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break;
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}
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if (ctx->checkWireAvail(next)) {
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for (auto pip : ctx->getPipsUphill(next)) {
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WireId src = ctx->getPipSrcWire(pip);
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if (backtrace.count(src))
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continue;
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backtrace[src] = pip;
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upstream.push(src);
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}
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}
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if (upstream.size() > 30000) {
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log_error("failed to route HPBX%02d00 to %s.%s\n", global_index, ctx->nameOfBel(user.cell->bel),
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user.port.c_str(ctx));
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}
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}
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// Set all the pips we found along the way
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WireId cursor = next;
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while (true) {
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auto fnd = backtrace.find(cursor);
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if (fnd == backtrace.end())
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break;
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ctx->bindPip(fnd->second, net, STRENGTH_LOCKED);
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cursor = ctx->getPipDstWire(fnd->second);
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}
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// If the global network inside the tile isn't already set up,
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// we also need to bind the buffers along the way
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if (!already_routed) {
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ctx->bindWire(next, net, STRENGTH_LOCKED);
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PipId tap_pip = find_tap_pip(next);
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NetInfo *tap_net = ctx->getBoundPipNet(tap_pip);
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if (tap_net == nullptr) {
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ctx->bindPip(tap_pip, net, STRENGTH_LOCKED);
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PipId spine_pip = find_spine_pip(ctx->getPipSrcWire(tap_pip));
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NetInfo *spine_net = ctx->getBoundPipNet(spine_pip);
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if (spine_net == nullptr) {
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ctx->bindPip(spine_pip, net, STRENGTH_LOCKED);
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} else {
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NPNR_ASSERT(spine_net == net);
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}
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} else {
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NPNR_ASSERT(tap_net == net);
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}
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}
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}
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bool is_global_io(CellInfo *io, std::string &glb_name)
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{
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std::string func_name = ctx->get_pio_function_name(io->bel);
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if (func_name.substr(0, 5) == "PCLKT") {
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func_name.erase(func_name.find('_'), 1);
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glb_name = "G_" + func_name;
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return true;
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}
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return false;
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}
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WireId get_global_wire(GlobalQuadrant quad, int network)
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{
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return ctx->get_wire_by_loc_basename(Location(0, 0),
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"G_" + get_quad_name(quad) + "PCLK" + std::to_string(network));
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}
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bool simple_router(NetInfo *net, WireId src, WireId dst, bool allow_fail = false)
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{
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std::queue<WireId> visit;
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dict<WireId, PipId> backtrace;
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visit.push(src);
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WireId cursor;
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while (true) {
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if (visit.empty() || visit.size() > 50000) {
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if (allow_fail)
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return false;
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log_error("cannot route global from %s to %s.\n", ctx->nameOfWire(src), ctx->nameOfWire(dst));
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}
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cursor = visit.front();
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visit.pop();
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NetInfo *bound = ctx->getBoundWireNet(cursor);
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if (bound == net) {
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} else if (bound != nullptr) {
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continue;
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}
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if (cursor == dst)
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break;
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for (auto dh : ctx->getPipsDownhill(cursor)) {
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WireId pipDst = ctx->getPipDstWire(dh);
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if (backtrace.count(pipDst))
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continue;
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backtrace[pipDst] = dh;
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visit.push(pipDst);
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}
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}
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while (true) {
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auto fnd = backtrace.find(cursor);
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if (fnd == backtrace.end())
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break;
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NetInfo *bound = ctx->getBoundWireNet(cursor);
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if (bound != nullptr) {
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NPNR_ASSERT(bound == net);
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break;
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}
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ctx->bindPip(fnd->second, net, STRENGTH_LOCKED);
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cursor = ctx->getPipSrcWire(fnd->second);
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}
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if (ctx->getBoundWireNet(src) == nullptr)
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ctx->bindWire(src, net, STRENGTH_LOCKED);
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return true;
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}
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bool route_onto_global(NetInfo *net, int network)
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{
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WireId glb_src;
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NPNR_ASSERT(net->driver.cell->type == id_DCCA || net->driver.cell->type == id_DCSC);
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glb_src = ctx->getNetinfoSourceWire(net);
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for (int quad = QUAD_UL; quad < QUAD_LR + 1; quad++) {
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WireId glb_dst = get_global_wire(GlobalQuadrant(quad), network);
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NPNR_ASSERT(glb_dst != WireId());
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bool routed = simple_router(net, glb_src, glb_dst);
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if (!routed)
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return false;
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}
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return true;
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}
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// Get DCC wirelength based on source
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wirelen_t get_dcc_wirelen(CellInfo *dcc, bool &dedicated_routing)
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{
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NetInfo *clki = dcc->ports.at((dcc->type == id_DCSC) ? id_CLK0 : id_CLKI).net;
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BelId drv_bel;
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const PortRef &drv = clki->driver;
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dedicated_routing = false;
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if (drv.cell == nullptr) {
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return 0;
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} else if (drv.cell->attrs.count(id_BEL)) {
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drv_bel = ctx->getBelByNameStr(drv.cell->attrs.at(id_BEL).as_string());
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} else {
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// Check if driver is a singleton
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BelId last_bel;
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bool singleton = true;
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for (auto bel : ctx->getBels()) {
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if (ctx->getBelType(bel) == drv.cell->type) {
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if (last_bel != BelId()) {
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singleton = false;
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break;
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}
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last_bel = bel;
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}
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}
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if (singleton && last_bel != BelId()) {
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drv_bel = last_bel;
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}
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}
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if (drv_bel == BelId()) {
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// Driver is not locked. Use standard metric
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float tns;
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return get_net_metric(ctx, clki, MetricType::WIRELENGTH, tns);
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} else {
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// Check for dedicated routing
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if (has_short_route(ctx->getBelPinWire(drv_bel, drv.port), ctx->getBelPinWire(dcc->bel, id_CLKI))) {
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// log_info("dedicated route %s -> %s\n", ctx->nameOfWire(ctx->getBelPinWire(drv_bel,
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// drv.port)), ctx->nameOfWire(dcc->bel));
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dedicated_routing = true;
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return 0;
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}
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// Driver is locked
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Loc dcc_loc = ctx->getBelLocation(dcc->bel);
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Loc drv_loc = ctx->getBelLocation(drv_bel);
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return std::abs(dcc_loc.x - drv_loc.x) + std::abs(dcc_loc.y - drv_loc.y);
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}
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}
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// Return true if a short (<5) route exists between two wires
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bool has_short_route(WireId src, WireId dst, int thresh = 7)
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{
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std::queue<WireId> visit;
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dict<WireId, PipId> backtrace;
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visit.push(src);
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WireId cursor;
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while (true) {
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if (visit.empty() || visit.size() > 10000) {
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// log_info ("dist %s -> %s = inf\n", ctx->nameOfWire(src),
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// ctx->nameOfWire(dst));
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return false;
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}
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cursor = visit.front();
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visit.pop();
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if (cursor == dst)
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break;
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for (auto dh : ctx->getPipsDownhill(cursor)) {
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WireId pipDst = ctx->getPipDstWire(dh);
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if (backtrace.count(pipDst))
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continue;
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backtrace[pipDst] = dh;
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visit.push(pipDst);
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}
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}
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int length = 0;
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while (true) {
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auto fnd = backtrace.find(cursor);
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if (fnd == backtrace.end())
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break;
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cursor = ctx->getPipSrcWire(fnd->second);
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length++;
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}
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// log_info ("dist %s -> %s = %d\n", ctx->nameOfWire(src), ctx->nameOfWire(dst),
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// length);
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return length < thresh;
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}
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pool<WireId> used_pclkcib;
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std::set<WireId> get_candidate_pclkcibs(BelId dcc)
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{
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std::set<WireId> candidates;
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WireId dcc_i = ctx->getBelPinWire(dcc, id_CLKI);
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WireId dcc_mux = ctx->getPipSrcWire(*(ctx->getPipsUphill(dcc_i).begin()));
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for (auto pip : ctx->getPipsUphill(dcc_mux)) {
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WireId src = ctx->getPipSrcWire(pip);
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std::string basename = ctx->nameOf(ctx->get_wire_basename(src));
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if (basename.find("QPCLKCIB") == std::string::npos)
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continue;
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candidates.insert(src);
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}
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return candidates;
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}
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// Attempt to place a DCC
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void place_dcc_dcs(CellInfo *dcc)
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{
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BelId best_bel;
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WireId best_bel_pclkcib;
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bool using_ce = dcc->getPort(id_CE) != nullptr;
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wirelen_t best_wirelen = 9999999;
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bool dedicated_routing = false;
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for (auto bel : ctx->getBels()) {
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if (ctx->getBelType(bel) == dcc->type && ctx->checkBelAvail(bel)) {
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std::string belname = ctx->loc_info(bel)->bel_data[bel.index].name.get();
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if (belname.at(0) == 'D' && using_ce)
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continue; // don't allow DCCs with CE at center
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ctx->bindBel(bel, dcc, STRENGTH_LOCKED);
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if (!ctx->isBelLocationValid(bel)) {
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ctx->unbindBel(bel);
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continue;
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}
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wirelen_t wirelen = get_dcc_wirelen(dcc, dedicated_routing);
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if (wirelen < best_wirelen) {
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if (dedicated_routing || dcc->type == id_DCSC) {
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best_bel_pclkcib = WireId();
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} else {
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bool found_pclkcib = false;
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for (WireId pclkcib : get_candidate_pclkcibs(bel)) {
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if (used_pclkcib.count(pclkcib))
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continue;
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found_pclkcib = true;
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best_bel_pclkcib = pclkcib;
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break;
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}
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if (!found_pclkcib)
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goto pclkcib_fail;
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}
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best_bel = bel;
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best_wirelen = wirelen;
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}
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pclkcib_fail:
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ctx->unbindBel(bel);
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}
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}
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NPNR_ASSERT(best_bel != BelId());
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ctx->bindBel(best_bel, dcc, STRENGTH_LOCKED);
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if (best_bel_pclkcib != WireId()) {
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used_pclkcib.insert(best_bel_pclkcib);
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if (ctx->verbose)
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log_info(" preliminary allocation of PCLKCIB '%s' to DCC '%s' at '%s'\n",
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ctx->nameOfWire(best_bel_pclkcib), ctx->nameOf(dcc), ctx->nameOfBel(best_bel));
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}
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}
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// Insert a DCC into a net to promote it to a global
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NetInfo *insert_dcc(NetInfo *net, CellInfo *dcs_cell = nullptr)
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{
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NetInfo *glbptr = nullptr;
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CellInfo *dccptr = nullptr;
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if (net->driver.cell != nullptr && (net->driver.cell->type == id_DCCA || net->driver.cell->type == id_DCSC)) {
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// Already have a DCC (such as clock gating)
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glbptr = net;
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dccptr = net->driver.cell;
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} else {
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auto dcc = create_ecp5_cell(ctx, id_DCCA, "$gbuf$" + net->name.str(ctx));
|
|
glbptr = ctx->createNet(ctx->id("$glbnet$" + net->name.str(ctx)));
|
|
glbptr->driver.cell = dcc.get();
|
|
glbptr->driver.port = id_CLKO;
|
|
dcc->ports[id_CLKO].net = glbptr;
|
|
std::vector<PortRef> keep_users;
|
|
for (auto user : net->users) {
|
|
if (dcs_cell != nullptr && user.cell != dcs_cell) {
|
|
// DCS DCC insertion mode
|
|
keep_users.push_back(user);
|
|
} else if (user.port == id_CLKFB) {
|
|
keep_users.push_back(user);
|
|
} else if (net->driver.cell->type == id_EXTREFB && user.cell->type == id_DCUA) {
|
|
keep_users.push_back(user);
|
|
} else if (is_logic_port(user)) {
|
|
keep_users.push_back(user);
|
|
} else {
|
|
user.cell->ports.at(user.port).net = glbptr;
|
|
user.cell->ports.at(user.port).user_idx = glbptr->users.add(user);
|
|
}
|
|
}
|
|
net->users.clear();
|
|
for (auto &usr : keep_users)
|
|
usr.cell->ports.at(usr.port).user_idx = net->users.add(usr);
|
|
|
|
dcc->connectPort(id_CLKI, net);
|
|
if (net->clkconstr) {
|
|
glbptr->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
|
|
glbptr->clkconstr->low = net->clkconstr->low;
|
|
glbptr->clkconstr->high = net->clkconstr->high;
|
|
glbptr->clkconstr->period = net->clkconstr->period;
|
|
}
|
|
dccptr = dcc.get();
|
|
ctx->cells[dcc->name] = std::move(dcc);
|
|
}
|
|
glbptr->attrs[id_ECP5_IS_GLOBAL] = 1;
|
|
if (str_or_default(dccptr->attrs, id_BEL, "") == "")
|
|
place_dcc_dcs(dccptr);
|
|
return glbptr;
|
|
}
|
|
|
|
int global_route_priority(const PortRef &load)
|
|
{
|
|
if (load.port == id_WCK || load.port == id_WRE)
|
|
return 90;
|
|
return 99;
|
|
}
|
|
|
|
Context *ctx;
|
|
|
|
public:
|
|
void promote_globals()
|
|
{
|
|
bool is_ooc = bool_or_default(ctx->settings, ctx->id("arch.ooc"));
|
|
log_info("Promoting globals...\n");
|
|
auto clocks = get_clocks();
|
|
for (auto clock : clocks) {
|
|
bool is_noglobal = bool_or_default(clock->attrs, id_noglobal, false) ||
|
|
bool_or_default(clock->attrs, id_ECP5_IS_GLOBAL, false);
|
|
if (is_noglobal)
|
|
continue;
|
|
log_info(" promoting clock net %s to global network\n", clock->name.c_str(ctx));
|
|
if (is_ooc) // Don't actually do anything in OOC mode, global routing will be done in the full design
|
|
clock->is_global = true;
|
|
else
|
|
insert_dcc(clock);
|
|
}
|
|
// Insert DCCs on DCS inputs, too
|
|
std::vector<CellInfo *> dcsc_cells;
|
|
for (auto &cell : ctx->cells) {
|
|
CellInfo *ci = cell.second.get();
|
|
if (ci->type == id_DCSC)
|
|
dcsc_cells.push_back(ci);
|
|
}
|
|
for (auto ci : dcsc_cells) {
|
|
for (auto port : {id_CLK0, id_CLK1}) {
|
|
NetInfo *net = ci->getPort(port);
|
|
if (net != nullptr)
|
|
insert_dcc(net, ci);
|
|
}
|
|
}
|
|
}
|
|
|
|
void route_globals()
|
|
{
|
|
log_info("Routing globals...\n");
|
|
std::set<int> all_globals, fab_globals;
|
|
for (int i = 0; i < 16; i++) {
|
|
all_globals.insert(i);
|
|
if (i < 8)
|
|
fab_globals.insert(i);
|
|
}
|
|
std::vector<std::pair<PortRef *, int>> toroute;
|
|
dict<int, NetInfo *> clocks;
|
|
for (auto &cell : ctx->cells) {
|
|
CellInfo *ci = cell.second.get();
|
|
if (ci->type == id_DCCA || ci->type == id_DCSC) {
|
|
NetInfo *clock = ci->ports.at((ci->type == id_DCSC) ? id_DCSOUT : id_CLKO).net;
|
|
NPNR_ASSERT(clock != nullptr);
|
|
bool drives_fabric = false;
|
|
for (auto &usr : clock->users) {
|
|
if (!is_clock_port(usr)) {
|
|
drives_fabric = true;
|
|
break;
|
|
}
|
|
}
|
|
int glbid;
|
|
if (drives_fabric) {
|
|
if (fab_globals.empty())
|
|
continue;
|
|
glbid = *(fab_globals.begin());
|
|
} else {
|
|
glbid = *(all_globals.begin());
|
|
}
|
|
all_globals.erase(glbid);
|
|
fab_globals.erase(glbid);
|
|
|
|
log_info(" routing clock net %s using global %d\n", clock->name.c_str(ctx), glbid);
|
|
bool routed = route_onto_global(clock, glbid);
|
|
NPNR_ASSERT(routed);
|
|
|
|
// WCK must have routing priority
|
|
for (auto &user : clock->users)
|
|
toroute.emplace_back(&user, glbid);
|
|
clocks[glbid] = clock;
|
|
}
|
|
}
|
|
std::sort(toroute.begin(), toroute.end(),
|
|
[this](const std::pair<PortRef *, int> &a, const std::pair<PortRef *, int> &b) {
|
|
return global_route_priority(*a.first) < global_route_priority(*b.first);
|
|
});
|
|
for (const auto &user : toroute) {
|
|
if (user.first->cell->type == id_DCSC && (user.first->port == id_CLK0 || user.first->port == id_CLK1)) {
|
|
// Special case, skips most of the typical global network
|
|
NetInfo *net = clocks.at(user.second);
|
|
simple_router(net, ctx->getNetinfoSourceWire(net), ctx->getNetinfoSinkWire(net, *(user.first), 0));
|
|
continue;
|
|
}
|
|
route_logic_tile_global(clocks.at(user.second), user.second, *user.first);
|
|
}
|
|
}
|
|
|
|
void route_eclk_sources()
|
|
{
|
|
// Try and use dedicated paths if possible
|
|
for (auto &cell : ctx->cells) {
|
|
CellInfo *ci = cell.second.get();
|
|
if (ci->type == id_ECLKSYNCB || ci->type == id_TRELLIS_ECLKBUF || ci->type == id_ECLKBRIDGECS) {
|
|
std::vector<IdString> pins;
|
|
if (ci->type == id_ECLKSYNCB || ci->type == id_TRELLIS_ECLKBUF) {
|
|
pins.push_back(id_ECLKI);
|
|
} else {
|
|
pins.push_back(id_CLK0);
|
|
pins.push_back(id_CLK1);
|
|
}
|
|
for (auto pin : pins) {
|
|
NetInfo *ni = ci->getPort(pin);
|
|
if (ni == nullptr)
|
|
continue;
|
|
log_info(" trying dedicated routing for edge clock source %s\n", ctx->nameOf(ni));
|
|
WireId src = ctx->getNetinfoSourceWire(ni);
|
|
WireId dst = ctx->getBelPinWire(ci->bel, pin);
|
|
std::queue<WireId> visit;
|
|
dict<WireId, PipId> backtrace;
|
|
visit.push(dst);
|
|
int iter = 0;
|
|
WireId cursor;
|
|
bool success = false;
|
|
// This is a best-effort pass, if it fails then still try general routing later
|
|
const int iter_max = 1000;
|
|
while (iter < iter_max && !visit.empty()) {
|
|
cursor = visit.front();
|
|
visit.pop();
|
|
++iter;
|
|
NetInfo *bound = ctx->getBoundWireNet(cursor);
|
|
if (bound != nullptr) {
|
|
if (bound == ni) {
|
|
success = true;
|
|
break;
|
|
} else {
|
|
continue;
|
|
}
|
|
}
|
|
if (cursor == src) {
|
|
ctx->bindWire(cursor, ni, STRENGTH_LOCKED);
|
|
success = true;
|
|
break;
|
|
}
|
|
for (auto uh : ctx->getPipsUphill(cursor)) {
|
|
if (!ctx->checkPipAvail(uh))
|
|
continue;
|
|
WireId src = ctx->getPipSrcWire(uh);
|
|
if (backtrace.count(src))
|
|
continue;
|
|
IdString basename = ctx->get_wire_basename(src);
|
|
// "ECLKCIB" wires are the junction with general routing
|
|
if (basename.str(ctx).find("ECLKCIB") != std::string::npos)
|
|
continue;
|
|
visit.push(src);
|
|
backtrace[src] = uh;
|
|
}
|
|
}
|
|
if (success) {
|
|
while (cursor != dst) {
|
|
PipId pip = backtrace.at(cursor);
|
|
ctx->bindPip(pip, ni, STRENGTH_LOCKED);
|
|
cursor = ctx->getPipDstWire(pip);
|
|
}
|
|
} else {
|
|
log_info(" no route found, general routing will be used.\n");
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
};
|
|
void promote_ecp5_globals(Context *ctx) { Ecp5GlobalRouter(ctx).promote_globals(); }
|
|
void route_ecp5_globals(Context *ctx)
|
|
{
|
|
Ecp5GlobalRouter router(ctx);
|
|
router.route_globals();
|
|
router.route_eclk_sources();
|
|
}
|
|
|
|
NEXTPNR_NAMESPACE_END
|