Adrien Prost-Boucle 0ce60c335a Himbaechel xilinx : DSP packing : Fix identification of cascaded ports and share identification code		2024-09-17 16:11:48 +02:00
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example	Make example more like other arch	2024-04-05 12:25:52 +02:00
gowin	Gowin. BUGFIX. Create all Clock Pips. (#1358)	2024-09-05 21:39:26 +01:00
xilinx	Himbaechel xilinx : DSP packing : Fix identification of cascaded ports and share identification code	2024-09-17 16:11:48 +02:00