1864 lines
22 KiB
C++
1864 lines
22 KiB
C++
X(A0)
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X(B0)
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X(C0)
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X(D0)
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X(A1)
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X(B1)
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X(C1)
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X(D1)
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X(M0)
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X(M1)
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X(FCI)
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X(FXA)
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X(FXB)
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X(CLK)
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X(LSR)
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X(CE)
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X(DI0)
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X(DI1)
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X(WD0)
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X(WD1)
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X(WAD0)
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X(WAD1)
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X(WAD2)
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X(WAD3)
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X(WRE)
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X(WCK)
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X(F0)
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X(Q0)
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X(F1)
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X(Q1)
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X(FCO)
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X(OFX0)
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X(OFX1)
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X(WDO0)
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X(WDO1)
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X(WDO2)
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X(WDO3)
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X(WADO0)
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X(WADO1)
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X(WADO2)
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X(WADO3)
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X(I)
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X(O)
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X(T)
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X(B)
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X(TRELLIS_SLICE)
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X(TRELLIS_IO)
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X(DCCA)
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X(CLKMUX)
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X(LSRMUX)
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X(SRMODE)
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X(CLKI)
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X(CLKO)
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X(DP16KD)
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X(DIA0)
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X(DIA1)
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X(DIA2)
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X(DIA3)
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X(DIA4)
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X(DIA5)
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X(DIA6)
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X(DIA7)
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X(DIA8)
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X(DIA9)
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X(DIA10)
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X(DIA11)
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X(DIA12)
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X(DIA13)
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X(DIA14)
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X(DIA15)
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X(DIA16)
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X(DIA17)
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X(ADA0)
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X(ADA1)
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X(ADA2)
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X(ADA3)
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X(ADA4)
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X(ADA5)
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X(ADA6)
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X(ADA7)
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X(ADA8)
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X(ADA9)
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X(ADA10)
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X(ADA11)
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X(ADA12)
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X(ADA13)
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X(CEA)
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X(OCEA)
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X(CLKA)
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X(WEA)
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X(CSA2)
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X(CSA1)
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X(CSA0)
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X(RSTA)
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X(DIB0)
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X(DIB1)
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X(DIB2)
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X(DIB3)
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X(DIB4)
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X(DIB5)
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X(DIB6)
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X(DIB7)
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X(DIB8)
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X(DIB9)
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X(DIB10)
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X(DIB11)
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X(DIB12)
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X(DIB13)
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X(DIB14)
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X(DIB15)
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X(DIB16)
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X(DIB17)
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X(ADB0)
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X(ADB1)
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X(ADB2)
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X(ADB3)
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X(ADB4)
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X(ADB5)
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X(ADB6)
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X(ADB7)
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X(ADB8)
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X(ADB9)
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X(ADB10)
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X(ADB11)
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X(ADB12)
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X(ADB13)
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X(CEB)
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X(OCEB)
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X(CLKB)
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X(WEB)
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X(CSB2)
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X(CSB1)
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X(CSB0)
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X(RSTB)
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X(DOA0)
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X(DOA1)
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X(DOA2)
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X(DOA3)
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X(DOA4)
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X(DOA5)
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X(DOA6)
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X(DOA7)
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X(DOA8)
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X(DOA9)
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X(DOA10)
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X(DOA11)
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X(DOA12)
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X(DOA13)
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X(DOA14)
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X(DOA15)
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X(DOA16)
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X(DOA17)
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X(DOB0)
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X(DOB1)
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X(DOB2)
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X(DOB3)
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X(DOB4)
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X(DOB5)
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X(DOB6)
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X(DOB7)
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X(DOB8)
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X(DOB9)
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X(DOB10)
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X(DOB11)
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X(DOB12)
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X(DOB13)
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X(DOB14)
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X(DOB15)
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X(DOB16)
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X(DOB17)
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X(MULT18X18D)
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X(A2)
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X(A3)
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X(A4)
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X(A5)
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X(A6)
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X(A7)
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X(A8)
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X(A9)
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X(A10)
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X(A11)
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X(A12)
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X(A13)
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X(A14)
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X(A15)
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X(A16)
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X(A17)
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X(B2)
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X(B3)
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X(B4)
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X(B5)
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X(B6)
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X(B7)
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X(B8)
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X(B9)
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X(B10)
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X(B11)
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X(B12)
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X(B13)
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X(B14)
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X(B15)
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X(B16)
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X(B17)
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X(C2)
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X(C3)
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X(C4)
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X(C5)
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X(C6)
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X(C7)
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X(C8)
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X(C9)
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X(C10)
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X(C11)
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X(C12)
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X(C13)
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X(C14)
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X(C15)
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X(C16)
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X(C17)
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X(SIGNEDA)
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X(SIGNEDB)
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X(SOURCEA)
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X(SOURCEB)
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X(CLK0)
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X(CLK1)
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X(CLK2)
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X(CLK3)
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X(CE0)
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X(CE1)
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X(CE2)
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X(CE3)
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X(RST0)
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X(RST1)
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X(RST2)
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X(RST3)
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X(SRIA0)
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X(SRIA1)
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X(SRIA2)
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X(SRIA3)
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X(SRIA4)
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X(SRIA5)
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X(SRIA6)
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X(SRIA7)
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X(SRIA8)
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X(SRIA9)
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X(SRIA10)
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X(SRIA11)
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X(SRIA12)
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X(SRIA13)
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X(SRIA14)
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X(SRIA15)
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X(SRIA16)
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X(SRIA17)
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X(SRIB0)
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X(SRIB1)
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X(SRIB2)
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X(SRIB3)
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X(SRIB4)
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X(SRIB5)
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X(SRIB6)
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X(SRIB7)
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X(SRIB8)
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X(SRIB9)
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X(SRIB10)
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X(SRIB11)
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X(SRIB12)
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X(SRIB13)
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X(SRIB14)
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X(SRIB15)
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X(SRIB16)
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X(SRIB17)
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X(SROA0)
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X(SROA1)
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X(SROA2)
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X(SROA3)
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X(SROA4)
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X(SROA5)
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X(SROA6)
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X(SROA7)
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X(SROA8)
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X(SROA9)
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X(SROA10)
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X(SROA11)
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X(SROA12)
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X(SROA13)
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X(SROA14)
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X(SROA15)
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X(SROA16)
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X(SROA17)
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X(SROB0)
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X(SROB1)
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X(SROB2)
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X(SROB3)
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X(SROB4)
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X(SROB5)
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X(SROB6)
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X(SROB7)
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X(SROB8)
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X(SROB9)
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X(SROB10)
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X(SROB11)
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X(SROB12)
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X(SROB13)
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X(SROB14)
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X(SROB15)
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X(SROB16)
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X(SROB17)
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X(ROA0)
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X(ROA1)
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X(ROA2)
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X(ROA3)
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X(ROA4)
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X(ROA5)
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X(ROA6)
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X(ROA7)
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X(ROA8)
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X(ROA9)
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X(ROA10)
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X(ROA11)
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X(ROA12)
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X(ROA13)
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X(ROA14)
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X(ROA15)
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X(ROA16)
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X(ROA17)
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X(ROB0)
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X(ROB1)
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X(ROB2)
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X(ROB3)
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X(ROB4)
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X(ROB5)
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X(ROB6)
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X(ROB7)
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X(ROB8)
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X(ROB9)
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X(ROB10)
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X(ROB11)
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X(ROB12)
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X(ROB13)
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X(ROB14)
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X(ROB15)
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X(ROB16)
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X(ROB17)
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X(ROC0)
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X(ROC1)
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X(ROC2)
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X(ROC3)
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X(ROC4)
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X(ROC5)
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X(ROC6)
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X(ROC7)
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X(ROC8)
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X(ROC9)
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X(ROC10)
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X(ROC11)
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X(ROC12)
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X(ROC13)
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X(ROC14)
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X(ROC15)
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X(ROC16)
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X(ROC17)
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X(P0)
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X(P1)
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X(P2)
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X(P3)
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X(P4)
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X(P5)
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X(P6)
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X(P7)
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X(P8)
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X(P9)
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X(P10)
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X(P11)
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X(P12)
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X(P13)
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X(P14)
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X(P15)
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X(P16)
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X(P17)
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X(P18)
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X(P19)
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X(P20)
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X(P21)
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X(P22)
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X(P23)
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X(P24)
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X(P25)
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X(P26)
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X(P27)
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X(P28)
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X(P29)
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X(P30)
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X(P31)
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X(P32)
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X(P33)
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X(P34)
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X(P35)
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X(SIGNEDP)
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X(ALU54B)
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X(SIGNEDIA)
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X(SIGNEDIB)
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X(SIGNEDCIN)
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X(A18)
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X(A19)
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X(A20)
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X(A21)
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X(A22)
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X(A23)
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X(A24)
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X(A25)
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X(A26)
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X(A27)
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X(A28)
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X(A29)
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X(A30)
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X(A31)
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X(A32)
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X(A33)
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X(A34)
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X(A35)
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X(B18)
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X(B19)
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X(B20)
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X(B21)
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X(B22)
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X(B23)
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X(B24)
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X(B25)
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X(B26)
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X(B27)
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X(B28)
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X(B29)
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X(B30)
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X(B31)
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X(B32)
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X(B33)
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X(B34)
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X(B35)
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X(C18)
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X(C19)
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X(C20)
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X(C21)
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X(C22)
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X(C23)
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X(C24)
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X(C25)
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X(C26)
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X(C27)
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X(C28)
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X(C29)
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X(C30)
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X(C31)
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X(C32)
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X(C33)
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X(C34)
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X(C35)
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X(C36)
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X(C37)
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X(C38)
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X(C39)
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X(C40)
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X(C41)
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X(C42)
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X(C43)
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X(C44)
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X(C45)
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X(C46)
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X(C47)
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X(C48)
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X(C49)
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X(C50)
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X(C51)
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X(C52)
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X(C53)
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X(CFB0)
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X(CFB1)
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X(CFB2)
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X(CFB3)
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X(CFB4)
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X(CFB5)
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X(CFB6)
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X(CFB7)
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X(CFB8)
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X(CFB9)
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X(CFB10)
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X(CFB11)
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X(CFB12)
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X(CFB13)
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X(CFB14)
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X(CFB15)
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X(CFB16)
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X(CFB17)
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X(CFB18)
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X(CFB19)
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X(CFB20)
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X(CFB21)
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X(CFB22)
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X(CFB23)
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X(CFB24)
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X(CFB25)
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X(CFB26)
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X(CFB27)
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X(CFB28)
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X(CFB29)
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X(CFB30)
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X(CFB31)
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X(CFB32)
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X(CFB33)
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X(CFB34)
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X(CFB35)
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X(CFB36)
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X(CFB37)
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X(CFB38)
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X(CFB39)
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X(CFB40)
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X(CFB41)
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X(CFB42)
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X(CFB43)
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X(CFB44)
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X(CFB45)
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X(CFB46)
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X(CFB47)
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X(CFB48)
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X(CFB49)
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X(CFB50)
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X(CFB51)
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X(CFB52)
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X(CFB53)
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X(MA0)
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X(MA1)
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X(MA2)
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X(MA3)
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X(MA4)
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X(MA5)
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X(MA6)
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X(MA7)
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X(MA8)
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X(MA9)
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X(MA10)
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X(MA11)
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X(MA12)
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X(MA13)
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X(MA14)
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X(MA15)
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X(MA16)
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X(MA17)
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X(MA18)
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X(MA19)
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X(MA20)
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X(MA21)
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X(MA22)
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X(MA23)
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X(MA24)
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X(MA25)
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X(MA26)
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X(MA27)
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X(MA28)
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X(MA29)
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X(MA30)
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X(MA31)
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X(MA32)
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X(MA33)
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X(MA34)
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X(MA35)
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X(MB0)
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X(MB1)
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X(MB2)
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X(MB3)
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X(MB4)
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X(MB5)
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X(MB6)
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X(MB7)
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X(MB8)
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X(MB9)
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X(MB10)
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X(MB11)
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X(MB12)
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X(MB13)
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X(MB14)
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X(MB15)
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X(MB16)
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X(MB17)
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X(MB18)
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X(MB19)
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X(MB20)
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X(MB21)
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X(MB22)
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X(MB23)
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X(MB24)
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X(MB25)
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X(MB26)
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X(MB27)
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X(MB28)
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X(MB29)
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X(MB30)
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X(MB31)
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X(MB32)
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X(MB33)
|
|
X(MB34)
|
|
X(MB35)
|
|
X(CIN0)
|
|
X(CIN1)
|
|
X(CIN2)
|
|
X(CIN3)
|
|
X(CIN4)
|
|
X(CIN5)
|
|
X(CIN6)
|
|
X(CIN7)
|
|
X(CIN8)
|
|
X(CIN9)
|
|
X(CIN10)
|
|
X(CIN11)
|
|
X(CIN12)
|
|
X(CIN13)
|
|
X(CIN14)
|
|
X(CIN15)
|
|
X(CIN16)
|
|
X(CIN17)
|
|
X(CIN18)
|
|
X(CIN19)
|
|
X(CIN20)
|
|
X(CIN21)
|
|
X(CIN22)
|
|
X(CIN23)
|
|
X(CIN24)
|
|
X(CIN25)
|
|
X(CIN26)
|
|
X(CIN27)
|
|
X(CIN28)
|
|
X(CIN29)
|
|
X(CIN30)
|
|
X(CIN31)
|
|
X(CIN32)
|
|
X(CIN33)
|
|
X(CIN34)
|
|
X(CIN35)
|
|
X(CIN36)
|
|
X(CIN37)
|
|
X(CIN38)
|
|
X(CIN39)
|
|
X(CIN40)
|
|
X(CIN41)
|
|
X(CIN42)
|
|
X(CIN43)
|
|
X(CIN44)
|
|
X(CIN45)
|
|
X(CIN46)
|
|
X(CIN47)
|
|
X(CIN48)
|
|
X(CIN49)
|
|
X(CIN50)
|
|
X(CIN51)
|
|
X(CIN52)
|
|
X(CIN53)
|
|
X(OP0)
|
|
X(OP1)
|
|
X(OP2)
|
|
X(OP3)
|
|
X(OP4)
|
|
X(OP5)
|
|
X(OP6)
|
|
X(OP7)
|
|
X(OP8)
|
|
X(OP9)
|
|
X(OP10)
|
|
X(R0)
|
|
X(R1)
|
|
X(R2)
|
|
X(R3)
|
|
X(R4)
|
|
X(R5)
|
|
X(R6)
|
|
X(R7)
|
|
X(R8)
|
|
X(R9)
|
|
X(R10)
|
|
X(R11)
|
|
X(R12)
|
|
X(R13)
|
|
X(R14)
|
|
X(R15)
|
|
X(R16)
|
|
X(R17)
|
|
X(R18)
|
|
X(R19)
|
|
X(R20)
|
|
X(R21)
|
|
X(R22)
|
|
X(R23)
|
|
X(R24)
|
|
X(R25)
|
|
X(R26)
|
|
X(R27)
|
|
X(R28)
|
|
X(R29)
|
|
X(R30)
|
|
X(R31)
|
|
X(R32)
|
|
X(R33)
|
|
X(R34)
|
|
X(R35)
|
|
X(R36)
|
|
X(R37)
|
|
X(R38)
|
|
X(R39)
|
|
X(R40)
|
|
X(R41)
|
|
X(R42)
|
|
X(R43)
|
|
X(R44)
|
|
X(R45)
|
|
X(R46)
|
|
X(R47)
|
|
X(R48)
|
|
X(R49)
|
|
X(R50)
|
|
X(R51)
|
|
X(R52)
|
|
X(R53)
|
|
X(CO0)
|
|
X(CO1)
|
|
X(CO2)
|
|
X(CO3)
|
|
X(CO4)
|
|
X(CO5)
|
|
X(CO6)
|
|
X(CO7)
|
|
X(CO8)
|
|
X(CO9)
|
|
X(CO10)
|
|
X(CO11)
|
|
X(CO12)
|
|
X(CO13)
|
|
X(CO14)
|
|
X(CO15)
|
|
X(CO16)
|
|
X(CO17)
|
|
X(CO18)
|
|
X(CO19)
|
|
X(CO20)
|
|
X(CO21)
|
|
X(CO22)
|
|
X(CO23)
|
|
X(CO24)
|
|
X(CO25)
|
|
X(CO26)
|
|
X(CO27)
|
|
X(CO28)
|
|
X(CO29)
|
|
X(CO30)
|
|
X(CO31)
|
|
X(CO32)
|
|
X(CO33)
|
|
X(CO34)
|
|
X(CO35)
|
|
X(CO36)
|
|
X(CO37)
|
|
X(CO38)
|
|
X(CO39)
|
|
X(CO40)
|
|
X(CO41)
|
|
X(CO42)
|
|
X(CO43)
|
|
X(CO44)
|
|
X(CO45)
|
|
X(CO46)
|
|
X(CO47)
|
|
X(CO48)
|
|
X(CO49)
|
|
X(CO50)
|
|
X(CO51)
|
|
X(CO52)
|
|
X(CO53)
|
|
X(EQZ)
|
|
X(EQZM)
|
|
X(EQOM)
|
|
X(EQPAT)
|
|
X(EQPATB)
|
|
X(OVER)
|
|
X(UNDER)
|
|
X(OVERUNDER)
|
|
X(SIGNEDR)
|
|
|
|
X(EHXPLLL)
|
|
X(CLKFB)
|
|
X(PHASESEL1)
|
|
X(PHASESEL0)
|
|
X(PHASEDIR)
|
|
X(PHASESTEP)
|
|
X(PHASELOADREG)
|
|
X(STDBY)
|
|
X(PLLWAKESYNC)
|
|
X(RST)
|
|
X(ENCLKOP)
|
|
X(ENCLKOS)
|
|
X(ENCLKOS2)
|
|
X(ENCLKOS3)
|
|
X(CLKOP)
|
|
X(CLKOS)
|
|
X(CLKOS2)
|
|
X(CLKOS3)
|
|
X(LOCK)
|
|
X(INTLOCK)
|
|
X(REFCLK)
|
|
X(CLKINTFB)
|
|
|
|
X(EXTREFB)
|
|
X(REFCLKP)
|
|
X(REFCLKN)
|
|
X(REFCLKO)
|
|
|
|
X(DCUA)
|
|
X(CH0_HDINP)
|
|
X(CH1_HDINP)
|
|
X(CH0_HDINN)
|
|
X(CH1_HDINN)
|
|
X(D_TXBIT_CLKP_FROM_ND)
|
|
X(D_TXBIT_CLKN_FROM_ND)
|
|
X(D_SYNC_ND)
|
|
X(D_TXPLL_LOL_FROM_ND)
|
|
X(CH0_RX_REFCLK)
|
|
X(CH1_RX_REFCLK)
|
|
X(CH0_FF_RXI_CLK)
|
|
X(CH1_FF_RXI_CLK)
|
|
X(CH0_FF_TXI_CLK)
|
|
X(CH1_FF_TXI_CLK)
|
|
X(CH0_FF_EBRD_CLK)
|
|
X(CH1_FF_EBRD_CLK)
|
|
X(CH0_FF_TX_D_0)
|
|
X(CH1_FF_TX_D_0)
|
|
X(CH0_FF_TX_D_1)
|
|
X(CH1_FF_TX_D_1)
|
|
X(CH0_FF_TX_D_2)
|
|
X(CH1_FF_TX_D_2)
|
|
X(CH0_FF_TX_D_3)
|
|
X(CH1_FF_TX_D_3)
|
|
X(CH0_FF_TX_D_4)
|
|
X(CH1_FF_TX_D_4)
|
|
X(CH0_FF_TX_D_5)
|
|
X(CH1_FF_TX_D_5)
|
|
X(CH0_FF_TX_D_6)
|
|
X(CH1_FF_TX_D_6)
|
|
X(CH0_FF_TX_D_7)
|
|
X(CH1_FF_TX_D_7)
|
|
X(CH0_FF_TX_D_8)
|
|
X(CH1_FF_TX_D_8)
|
|
X(CH0_FF_TX_D_9)
|
|
X(CH1_FF_TX_D_9)
|
|
X(CH0_FF_TX_D_10)
|
|
X(CH1_FF_TX_D_10)
|
|
X(CH0_FF_TX_D_11)
|
|
X(CH1_FF_TX_D_11)
|
|
X(CH0_FF_TX_D_12)
|
|
X(CH1_FF_TX_D_12)
|
|
X(CH0_FF_TX_D_13)
|
|
X(CH1_FF_TX_D_13)
|
|
X(CH0_FF_TX_D_14)
|
|
X(CH1_FF_TX_D_14)
|
|
X(CH0_FF_TX_D_15)
|
|
X(CH1_FF_TX_D_15)
|
|
X(CH0_FF_TX_D_16)
|
|
X(CH1_FF_TX_D_16)
|
|
X(CH0_FF_TX_D_17)
|
|
X(CH1_FF_TX_D_17)
|
|
X(CH0_FF_TX_D_18)
|
|
X(CH1_FF_TX_D_18)
|
|
X(CH0_FF_TX_D_19)
|
|
X(CH1_FF_TX_D_19)
|
|
X(CH0_FF_TX_D_20)
|
|
X(CH1_FF_TX_D_20)
|
|
X(CH0_FF_TX_D_21)
|
|
X(CH1_FF_TX_D_21)
|
|
X(CH0_FF_TX_D_22)
|
|
X(CH1_FF_TX_D_22)
|
|
X(CH0_FF_TX_D_23)
|
|
X(CH1_FF_TX_D_23)
|
|
X(CH0_FFC_EI_EN)
|
|
X(CH1_FFC_EI_EN)
|
|
X(CH0_FFC_PCIE_DET_EN)
|
|
X(CH1_FFC_PCIE_DET_EN)
|
|
X(CH0_FFC_PCIE_CT)
|
|
X(CH1_FFC_PCIE_CT)
|
|
X(CH0_FFC_SB_INV_RX)
|
|
X(CH1_FFC_SB_INV_RX)
|
|
X(CH0_FFC_ENABLE_CGALIGN)
|
|
X(CH1_FFC_ENABLE_CGALIGN)
|
|
X(CH0_FFC_SIGNAL_DETECT)
|
|
X(CH1_FFC_SIGNAL_DETECT)
|
|
X(CH0_FFC_FB_LOOPBACK)
|
|
X(CH1_FFC_FB_LOOPBACK)
|
|
X(CH0_FFC_SB_PFIFO_LP)
|
|
X(CH1_FFC_SB_PFIFO_LP)
|
|
X(CH0_FFC_PFIFO_CLR)
|
|
X(CH1_FFC_PFIFO_CLR)
|
|
X(CH0_FFC_RATE_MODE_RX)
|
|
X(CH1_FFC_RATE_MODE_RX)
|
|
X(CH0_FFC_RATE_MODE_TX)
|
|
X(CH1_FFC_RATE_MODE_TX)
|
|
X(CH0_FFC_DIV11_MODE_RX)
|
|
X(CH1_FFC_DIV11_MODE_RX)
|
|
X(CH0_FFC_RX_GEAR_MODE)
|
|
X(CH1_FFC_RX_GEAR_MODE)
|
|
X(CH0_FFC_TX_GEAR_MODE)
|
|
X(CH1_FFC_TX_GEAR_MODE)
|
|
X(CH0_FFC_DIV11_MODE_TX)
|
|
X(CH1_FFC_DIV11_MODE_TX)
|
|
X(CH0_FFC_LDR_CORE2TX_EN)
|
|
X(CH1_FFC_LDR_CORE2TX_EN)
|
|
X(CH0_FFC_LANE_TX_RST)
|
|
X(CH1_FFC_LANE_TX_RST)
|
|
X(CH0_FFC_LANE_RX_RST)
|
|
X(CH1_FFC_LANE_RX_RST)
|
|
X(CH0_FFC_RRST)
|
|
X(CH1_FFC_RRST)
|
|
X(CH0_FFC_TXPWDNB)
|
|
X(CH1_FFC_TXPWDNB)
|
|
X(CH0_FFC_RXPWDNB)
|
|
X(CH1_FFC_RXPWDNB)
|
|
X(CH0_LDR_CORE2TX)
|
|
X(CH1_LDR_CORE2TX)
|
|
X(D_SCIWDATA0)
|
|
X(D_SCIWDATA1)
|
|
X(D_SCIWDATA2)
|
|
X(D_SCIWDATA3)
|
|
X(D_SCIWDATA4)
|
|
X(D_SCIWDATA5)
|
|
X(D_SCIWDATA6)
|
|
X(D_SCIWDATA7)
|
|
X(D_SCIADDR0)
|
|
X(D_SCIADDR1)
|
|
X(D_SCIADDR2)
|
|
X(D_SCIADDR3)
|
|
X(D_SCIADDR4)
|
|
X(D_SCIADDR5)
|
|
X(D_SCIENAUX)
|
|
X(D_SCISELAUX)
|
|
X(CH0_SCIEN)
|
|
X(CH1_SCIEN)
|
|
X(CH0_SCISEL)
|
|
X(CH1_SCISEL)
|
|
X(D_SCIRD)
|
|
X(D_SCIWSTN)
|
|
X(D_CYAWSTN)
|
|
X(D_FFC_SYNC_TOGGLE)
|
|
X(D_FFC_DUAL_RST)
|
|
X(D_FFC_MACRO_RST)
|
|
X(D_FFC_MACROPDB)
|
|
X(D_FFC_TRST)
|
|
X(CH0_FFC_CDR_EN_BITSLIP)
|
|
X(CH1_FFC_CDR_EN_BITSLIP)
|
|
X(D_SCAN_ENABLE)
|
|
X(D_SCAN_IN_0)
|
|
X(D_SCAN_IN_1)
|
|
X(D_SCAN_IN_2)
|
|
X(D_SCAN_IN_3)
|
|
X(D_SCAN_IN_4)
|
|
X(D_SCAN_IN_5)
|
|
X(D_SCAN_IN_6)
|
|
X(D_SCAN_IN_7)
|
|
X(D_SCAN_MODE)
|
|
X(D_SCAN_RESET)
|
|
X(D_CIN0)
|
|
X(D_CIN1)
|
|
X(D_CIN2)
|
|
X(D_CIN3)
|
|
X(D_CIN4)
|
|
X(D_CIN5)
|
|
X(D_CIN6)
|
|
X(D_CIN7)
|
|
X(D_CIN8)
|
|
X(D_CIN9)
|
|
X(D_CIN10)
|
|
X(D_CIN11)
|
|
X(CH0_HDOUTP)
|
|
X(CH1_HDOUTP)
|
|
X(CH0_HDOUTN)
|
|
X(CH1_HDOUTN)
|
|
X(D_TXBIT_CLKP_TO_ND)
|
|
X(D_TXBIT_CLKN_TO_ND)
|
|
X(D_SYNC_PULSE2ND)
|
|
X(D_TXPLL_LOL_TO_ND)
|
|
X(CH0_FF_RX_F_CLK)
|
|
X(CH1_FF_RX_F_CLK)
|
|
X(CH0_FF_RX_H_CLK)
|
|
X(CH1_FF_RX_H_CLK)
|
|
X(CH0_FF_TX_F_CLK)
|
|
X(CH1_FF_TX_F_CLK)
|
|
X(CH0_FF_TX_H_CLK)
|
|
X(CH1_FF_TX_H_CLK)
|
|
X(CH0_FF_RX_PCLK)
|
|
X(CH1_FF_RX_PCLK)
|
|
X(CH0_FF_TX_PCLK)
|
|
X(CH1_FF_TX_PCLK)
|
|
X(CH0_FF_RX_D_0)
|
|
X(CH1_FF_RX_D_0)
|
|
X(CH0_FF_RX_D_1)
|
|
X(CH1_FF_RX_D_1)
|
|
X(CH0_FF_RX_D_2)
|
|
X(CH1_FF_RX_D_2)
|
|
X(CH0_FF_RX_D_3)
|
|
X(CH1_FF_RX_D_3)
|
|
X(CH0_FF_RX_D_4)
|
|
X(CH1_FF_RX_D_4)
|
|
X(CH0_FF_RX_D_5)
|
|
X(CH1_FF_RX_D_5)
|
|
X(CH0_FF_RX_D_6)
|
|
X(CH1_FF_RX_D_6)
|
|
X(CH0_FF_RX_D_7)
|
|
X(CH1_FF_RX_D_7)
|
|
X(CH0_FF_RX_D_8)
|
|
X(CH1_FF_RX_D_8)
|
|
X(CH0_FF_RX_D_9)
|
|
X(CH1_FF_RX_D_9)
|
|
X(CH0_FF_RX_D_10)
|
|
X(CH1_FF_RX_D_10)
|
|
X(CH0_FF_RX_D_11)
|
|
X(CH1_FF_RX_D_11)
|
|
X(CH0_FF_RX_D_12)
|
|
X(CH1_FF_RX_D_12)
|
|
X(CH0_FF_RX_D_13)
|
|
X(CH1_FF_RX_D_13)
|
|
X(CH0_FF_RX_D_14)
|
|
X(CH1_FF_RX_D_14)
|
|
X(CH0_FF_RX_D_15)
|
|
X(CH1_FF_RX_D_15)
|
|
X(CH0_FF_RX_D_16)
|
|
X(CH1_FF_RX_D_16)
|
|
X(CH0_FF_RX_D_17)
|
|
X(CH1_FF_RX_D_17)
|
|
X(CH0_FF_RX_D_18)
|
|
X(CH1_FF_RX_D_18)
|
|
X(CH0_FF_RX_D_19)
|
|
X(CH1_FF_RX_D_19)
|
|
X(CH0_FF_RX_D_20)
|
|
X(CH1_FF_RX_D_20)
|
|
X(CH0_FF_RX_D_21)
|
|
X(CH1_FF_RX_D_21)
|
|
X(CH0_FF_RX_D_22)
|
|
X(CH1_FF_RX_D_22)
|
|
X(CH0_FF_RX_D_23)
|
|
X(CH1_FF_RX_D_23)
|
|
X(CH0_FFS_PCIE_DONE)
|
|
X(CH1_FFS_PCIE_DONE)
|
|
X(CH0_FFS_PCIE_CON)
|
|
X(CH1_FFS_PCIE_CON)
|
|
X(CH0_FFS_RLOS)
|
|
X(CH1_FFS_RLOS)
|
|
X(CH0_FFS_LS_SYNC_STATUS)
|
|
X(CH1_FFS_LS_SYNC_STATUS)
|
|
X(CH0_FFS_CC_UNDERRUN)
|
|
X(CH1_FFS_CC_UNDERRUN)
|
|
X(CH0_FFS_CC_OVERRUN)
|
|
X(CH1_FFS_CC_OVERRUN)
|
|
X(CH0_FFS_RXFBFIFO_ERROR)
|
|
X(CH1_FFS_RXFBFIFO_ERROR)
|
|
X(CH0_FFS_TXFBFIFO_ERROR)
|
|
X(CH1_FFS_TXFBFIFO_ERROR)
|
|
X(CH0_FFS_RLOL)
|
|
X(CH1_FFS_RLOL)
|
|
X(CH0_FFS_SKP_ADDED)
|
|
X(CH1_FFS_SKP_ADDED)
|
|
X(CH0_FFS_SKP_DELETED)
|
|
X(CH1_FFS_SKP_DELETED)
|
|
X(CH0_LDR_RX2CORE)
|
|
X(CH1_LDR_RX2CORE)
|
|
X(D_SCIRDATA0)
|
|
X(D_SCIRDATA1)
|
|
X(D_SCIRDATA2)
|
|
X(D_SCIRDATA3)
|
|
X(D_SCIRDATA4)
|
|
X(D_SCIRDATA5)
|
|
X(D_SCIRDATA6)
|
|
X(D_SCIRDATA7)
|
|
X(D_SCIINT)
|
|
X(D_SCAN_OUT_0)
|
|
X(D_SCAN_OUT_1)
|
|
X(D_SCAN_OUT_2)
|
|
X(D_SCAN_OUT_3)
|
|
X(D_SCAN_OUT_4)
|
|
X(D_SCAN_OUT_5)
|
|
X(D_SCAN_OUT_6)
|
|
X(D_SCAN_OUT_7)
|
|
X(D_COUT0)
|
|
X(D_COUT1)
|
|
X(D_COUT2)
|
|
X(D_COUT3)
|
|
X(D_COUT4)
|
|
X(D_COUT5)
|
|
X(D_COUT6)
|
|
X(D_COUT7)
|
|
X(D_COUT8)
|
|
X(D_COUT9)
|
|
X(D_COUT10)
|
|
X(D_COUT11)
|
|
X(D_COUT12)
|
|
X(D_COUT13)
|
|
X(D_COUT14)
|
|
X(D_COUT15)
|
|
X(D_COUT16)
|
|
X(D_COUT17)
|
|
X(D_COUT18)
|
|
X(D_COUT19)
|
|
X(D_REFCLKI)
|
|
X(D_FFS_PLOL)
|
|
|
|
X(PCSCLKDIV)
|
|
X(SEL2)
|
|
X(SEL1)
|
|
X(SEL0)
|
|
X(CDIV1)
|
|
|
|
X(DP16KD_REGMODE_A_NOREG_REGMODE_B_NOREG)
|
|
X(DP16KD_REGMODE_A_NOREG_REGMODE_B_OUTREG)
|
|
X(DP16KD_REGMODE_A_OUTREG_REGMODE_B_NOREG)
|
|
X(DP16KD_REGMODE_A_OUTREG_REGMODE_B_OUTREG)
|
|
X(DP16KD_WRITEMODE_A_NORMAL_WRITEMODE_B_NORMAL)
|
|
X(DP16KD_WRITEMODE_A_NORMAL_WRITEMODE_B_READBEFOREWRITE)
|
|
X(DP16KD_WRITEMODE_A_NORMAL_WRITEMODE_B_WRITETHROUGH)
|
|
X(PIO_IOTYPE_LVCMOS12)
|
|
X(PIO_IOTYPE_LVCMOS15)
|
|
X(PIO_IOTYPE_LVCMOS18)
|
|
X(PIO_IOTYPE_LVCMOS25)
|
|
X(PIO_IOTYPE_LVCMOS33)
|
|
X(PIO_IOTYPE_LVDS)
|
|
X(PIO_IOTYPE_SSTL15_I)
|
|
X(PIO_IOTYPE_SSTL15_II)
|
|
X(PIO_IOTYPE_SSTL18_I)
|
|
X(PIO_IOTYPE_SSTL18_II)
|
|
X(SCCU2C)
|
|
X(SDPRAME)
|
|
X(SLOGICB)
|
|
X(SRAMWB)
|
|
X(PAD)
|
|
X(PADDI)
|
|
X(PADDO)
|
|
X(PADDT)
|
|
|
|
X(IOLOGIC)
|
|
X(SIOLOGIC)
|
|
X(DI)
|
|
X(IOLDO)
|
|
X(IOLDOD)
|
|
X(IOLDOI)
|
|
X(IOLTO)
|
|
X(INDD)
|
|
X(LOADN)
|
|
X(MOVE)
|
|
X(DIRECTION)
|
|
X(TSDATA0)
|
|
X(TXDATA0)
|
|
X(TXDATA1)
|
|
X(RXDATA0)
|
|
X(RXDATA1)
|
|
X(INFF)
|
|
X(CFLAG)
|
|
X(ECLK)
|
|
X(TSDATA1)
|
|
X(TXDATA2)
|
|
X(TXDATA3)
|
|
X(RXDATA2)
|
|
X(RXDATA3)
|
|
X(TXDATA4)
|
|
X(TXDATA5)
|
|
X(TXDATA6)
|
|
X(RXDATA4)
|
|
X(RXDATA5)
|
|
X(RXDATA6)
|
|
X(DQSR90)
|
|
X(DQSW270)
|
|
X(DQSW)
|
|
X(RDPNTR0)
|
|
X(RDPNTR1)
|
|
X(RDPNTR2)
|
|
X(WRPNTR0)
|
|
X(WRPNTR1)
|
|
X(WRPNTR2)
|
|
X(SLIP)
|
|
|
|
X(GSR)
|
|
|
|
X(JTAGG)
|
|
X(TCK)
|
|
X(TMS)
|
|
X(TDI)
|
|
X(JTDO2)
|
|
X(JTDO1)
|
|
X(TDO)
|
|
X(JTDI)
|
|
X(JTCK)
|
|
X(JRTI2)
|
|
X(JRTI1)
|
|
X(JSHIFT)
|
|
X(JUPDATE)
|
|
X(JRSTN)
|
|
X(JCE2)
|
|
X(JCE1)
|
|
|
|
X(OSCG)
|
|
X(OSC)
|
|
X(SEDSTDBY)
|
|
|
|
X(SEDGA)
|
|
X(SEDENABLE)
|
|
X(SEDSTART)
|
|
X(SEDFRCERR)
|
|
X(SEDDONE)
|
|
X(SEDINPROG)
|
|
X(SEDERR)
|
|
|
|
X(DTR)
|
|
X(STARTPULSE)
|
|
X(DTROUT0)
|
|
X(DTROUT1)
|
|
X(DTROUT2)
|
|
X(DTROUT3)
|
|
X(DTROUT4)
|
|
X(DTROUT5)
|
|
X(DTROUT6)
|
|
X(DTROUT7)
|
|
|
|
X(USRMCLK)
|
|
|
|
X(CLKDIVF)
|
|
X(ALIGNWD)
|
|
X(CDIVX)
|
|
|
|
X(ECLKSYNCB)
|
|
X(ECLKI)
|
|
X(STOP)
|
|
X(ECLKO)
|
|
|
|
X(DLLDELD)
|
|
X(A)
|
|
X(DDRDEL)
|
|
X(Z)
|
|
|
|
X(DDRDLL)
|
|
X(UDDCNTLN)
|
|
X(FREEZE)
|
|
X(DIVOSC)
|
|
X(DCNTL0)
|
|
X(DCNTL1)
|
|
X(DCNTL2)
|
|
X(DCNTL3)
|
|
X(DCNTL4)
|
|
X(DCNTL5)
|
|
X(DCNTL6)
|
|
X(DCNTL7)
|
|
|
|
X(DQSBUFM)
|
|
X(DQSI)
|
|
X(READ1)
|
|
X(READ0)
|
|
X(READCLKSEL2)
|
|
X(READCLKSEL1)
|
|
X(READCLKSEL0)
|
|
X(DYNDELAY0)
|
|
X(DYNDELAY1)
|
|
X(DYNDELAY2)
|
|
X(DYNDELAY3)
|
|
X(DYNDELAY4)
|
|
X(DYNDELAY5)
|
|
X(DYNDELAY6)
|
|
X(DYNDELAY7)
|
|
X(PAUSE)
|
|
X(RDLOADN)
|
|
X(RDMOVE)
|
|
X(RDDIRECTION)
|
|
X(WRLOADN)
|
|
X(WRMOVE)
|
|
X(WRDIRECTION)
|
|
X(DATAVALID)
|
|
X(BURSTDET)
|
|
X(RDCFLAG)
|
|
X(WRCFLAG)
|
|
X(SCLK)
|
|
|
|
X(TRELLIS_ECLKBUF)
|
|
|
|
X(MULT18X18D_REGS_ALL)
|
|
X(MULT18X18D_REGS_INPUT)
|
|
X(MULT18X18D_REGS_NONE)
|
|
X(MULT18X18D_REGS_OUTPUT)
|
|
X(MULT18X18D_REGS_PIPELINE)
|
|
X(P)
|
|
|
|
X(ECLKBRIDGECS)
|
|
X(SEL)
|
|
X(ECSOUT)
|
|
|
|
X(WIRE_TYPE_NONE)
|
|
X(WIRE_TYPE_SLICE)
|
|
X(WIRE_TYPE_DQS)
|
|
X(WIRE_TYPE_IOLOGIC)
|
|
X(WIRE_TYPE_SIOLOGIC)
|
|
X(WIRE_TYPE_PIO)
|
|
X(WIRE_TYPE_EBR)
|
|
X(WIRE_TYPE_MULT18)
|
|
X(WIRE_TYPE_ALU54)
|
|
X(WIRE_TYPE_DDRDLL)
|
|
X(WIRE_TYPE_CCLK)
|
|
X(WIRE_TYPE_EXTREF)
|
|
X(WIRE_TYPE_DCU)
|
|
X(WIRE_TYPE_PLL)
|
|
X(WIRE_TYPE_SED)
|
|
X(WIRE_TYPE_OSC)
|
|
X(WIRE_TYPE_JTAG)
|
|
X(WIRE_TYPE_GSR)
|
|
X(WIRE_TYPE_DTR)
|
|
X(WIRE_TYPE_PCSCLKDIV)
|
|
|
|
X(WIRE_TYPE_H00)
|
|
X(WIRE_TYPE_H01)
|
|
X(WIRE_TYPE_H02)
|
|
X(WIRE_TYPE_H06)
|
|
X(WIRE_TYPE_V00)
|
|
X(WIRE_TYPE_V01)
|
|
X(WIRE_TYPE_V02)
|
|
X(WIRE_TYPE_V06)
|
|
|
|
X(WIRE_TYPE_G_HPBX)
|
|
X(WIRE_TYPE_G_VPTX)
|
|
X(WIRE_TYPE_L_HPBX)
|
|
X(WIRE_TYPE_R_HPBX)
|
|
|
|
X(IOLOGIC_MODE_IDDRX1F)
|
|
X(IOLOGIC_MODE_IDDRX2F)
|
|
X(IOLOGIC_MODE_IREG)
|
|
X(IOLOGIC_MODE_ODDRX1F)
|
|
X(IOLOGIC_MODE_ODDRX2F)
|
|
X(IOLOGIC_MODE_OREG)
|
|
X(IOLOGIC_MODE_TSREG)
|
|
|
|
X(DCSC)
|
|
X(DCSOUT)
|
|
X(MODESEL)
|
|
|
|
X(ALUT)
|
|
X(ASYNC_RESET_RELEASE)
|
|
X(BEL)
|
|
X(BLUT)
|
|
X(C)
|
|
X(CCU2C)
|
|
X(CCU2_INJECT1_0)
|
|
X(CCU2_INJECT1_1)
|
|
X(CEAMUX)
|
|
X(CEBMUX)
|
|
X(CEIMUX)
|
|
X(CEMUX)
|
|
X(CEOMUX)
|
|
X(CER)
|
|
X(CEW)
|
|
X(CH0_AUTO_CALIB_EN)
|
|
X(CH0_AUTO_FACQ_EN)
|
|
X(CH0_BAND_THRESHOLD)
|
|
X(CH0_CALIB_CK_MODE)
|
|
X(CH0_CC_MATCH_1)
|
|
X(CH0_CC_MATCH_2)
|
|
X(CH0_CC_MATCH_3)
|
|
X(CH0_CC_MATCH_4)
|
|
X(CH0_CDR_CNT4SEL)
|
|
X(CH0_CDR_CNT8SEL)
|
|
X(CH0_CTC_BYPASS)
|
|
X(CH0_DCOATDCFG)
|
|
X(CH0_DCOATDDLY)
|
|
X(CH0_DCOBYPSATD)
|
|
X(CH0_DCOCALDIV)
|
|
X(CH0_DCOCTLGI)
|
|
X(CH0_DCODISBDAVOID)
|
|
X(CH0_DCOFLTDAC)
|
|
X(CH0_DCOFTNRG)
|
|
X(CH0_DCOIOSTUNE)
|
|
X(CH0_DCOITUNE)
|
|
X(CH0_DCOITUNE4LSB)
|
|
X(CH0_DCOIUPDNX2)
|
|
X(CH0_DCONUOFLSB)
|
|
X(CH0_DCOSCALEI)
|
|
X(CH0_DCOSTARTVAL)
|
|
X(CH0_DCOSTEP)
|
|
X(CH0_DEC_BYPASS)
|
|
X(CH0_ENABLE_CG_ALIGN)
|
|
X(CH0_ENC_BYPASS)
|
|
X(CH0_FF_RX_F_CLK_DIS)
|
|
X(CH0_FF_RX_H_CLK_EN)
|
|
X(CH0_FF_TX_F_CLK_DIS)
|
|
X(CH0_FF_TX_H_CLK_EN)
|
|
X(CH0_GE_AN_ENABLE)
|
|
X(CH0_INVERT_RX)
|
|
X(CH0_INVERT_TX)
|
|
X(CH0_LDR_CORE2TX_SEL)
|
|
X(CH0_LDR_RX2CORE_SEL)
|
|
X(CH0_LEQ_OFFSET_SEL)
|
|
X(CH0_LEQ_OFFSET_TRIM)
|
|
X(CH0_LSM_DISABLE)
|
|
X(CH0_MATCH_2_ENABLE)
|
|
X(CH0_MATCH_4_ENABLE)
|
|
X(CH0_MIN_IPG_CNT)
|
|
X(CH0_PCIE_EI_EN)
|
|
X(CH0_PCIE_MODE)
|
|
X(CH0_PCS_DET_TIME_SEL)
|
|
X(CH0_PDEN_SEL)
|
|
X(CH0_PRBS_ENABLE)
|
|
X(CH0_PRBS_LOCK)
|
|
X(CH0_PRBS_SELECTION)
|
|
X(CH0_RATE_MODE_RX)
|
|
X(CH0_RATE_MODE_TX)
|
|
X(CH0_RCV_DCC_EN)
|
|
X(CH0_REG_BAND_OFFSET)
|
|
X(CH0_REG_BAND_SEL)
|
|
X(CH0_REG_IDAC_EN)
|
|
X(CH0_REG_IDAC_SEL)
|
|
X(CH0_REQ_EN)
|
|
X(CH0_REQ_LVL_SET)
|
|
X(CH0_RIO_MODE)
|
|
X(CH0_RLOS_SEL)
|
|
X(CH0_RPWDNB)
|
|
X(CH0_RTERM_RX)
|
|
X(CH0_RTERM_TX)
|
|
X(CH0_RXIN_CM)
|
|
X(CH0_RXTERM_CM)
|
|
X(CH0_RX_DCO_CK_DIV)
|
|
X(CH0_RX_DIV11_SEL)
|
|
X(CH0_RX_GEAR_BYPASS)
|
|
X(CH0_RX_GEAR_MODE)
|
|
X(CH0_RX_LOS_CEQ)
|
|
X(CH0_RX_LOS_EN)
|
|
X(CH0_RX_LOS_HYST_EN)
|
|
X(CH0_RX_LOS_LVL)
|
|
X(CH0_RX_RATE_SEL)
|
|
X(CH0_RX_SB_BYPASS)
|
|
X(CH0_SB_BYPASS)
|
|
X(CH0_SEL_SD_RX_CLK)
|
|
X(CH0_TDRV_DAT_SEL)
|
|
X(CH0_TDRV_POST_EN)
|
|
X(CH0_TDRV_PRE_EN)
|
|
X(CH0_TDRV_SLICE0_CUR)
|
|
X(CH0_TDRV_SLICE0_SEL)
|
|
X(CH0_TDRV_SLICE1_CUR)
|
|
X(CH0_TDRV_SLICE1_SEL)
|
|
X(CH0_TDRV_SLICE2_CUR)
|
|
X(CH0_TDRV_SLICE2_SEL)
|
|
X(CH0_TDRV_SLICE3_CUR)
|
|
X(CH0_TDRV_SLICE3_SEL)
|
|
X(CH0_TDRV_SLICE4_CUR)
|
|
X(CH0_TDRV_SLICE4_SEL)
|
|
X(CH0_TDRV_SLICE5_CUR)
|
|
X(CH0_TDRV_SLICE5_SEL)
|
|
X(CH0_TPWDNB)
|
|
X(CH0_TX_CM_SEL)
|
|
X(CH0_TX_DIV11_SEL)
|
|
X(CH0_TX_GEAR_BYPASS)
|
|
X(CH0_TX_GEAR_MODE)
|
|
X(CH0_TX_POST_SIGN)
|
|
X(CH0_TX_PRE_SIGN)
|
|
X(CH0_UC_MODE)
|
|
X(CH0_UDF_COMMA_A)
|
|
X(CH0_UDF_COMMA_B)
|
|
X(CH0_UDF_COMMA_MASK)
|
|
X(CH0_WA_BYPASS)
|
|
X(CH0_WA_MODE)
|
|
X(CH1_AUTO_CALIB_EN)
|
|
X(CH1_AUTO_FACQ_EN)
|
|
X(CH1_BAND_THRESHOLD)
|
|
X(CH1_CALIB_CK_MODE)
|
|
X(CH1_CC_MATCH_1)
|
|
X(CH1_CC_MATCH_2)
|
|
X(CH1_CC_MATCH_3)
|
|
X(CH1_CC_MATCH_4)
|
|
X(CH1_CDR_CNT4SEL)
|
|
X(CH1_CDR_CNT8SEL)
|
|
X(CH1_CTC_BYPASS)
|
|
X(CH1_DCOATDCFG)
|
|
X(CH1_DCOATDDLY)
|
|
X(CH1_DCOBYPSATD)
|
|
X(CH1_DCOCALDIV)
|
|
X(CH1_DCOCTLGI)
|
|
X(CH1_DCODISBDAVOID)
|
|
X(CH1_DCOFLTDAC)
|
|
X(CH1_DCOFTNRG)
|
|
X(CH1_DCOIOSTUNE)
|
|
X(CH1_DCOITUNE)
|
|
X(CH1_DCOITUNE4LSB)
|
|
X(CH1_DCOIUPDNX2)
|
|
X(CH1_DCONUOFLSB)
|
|
X(CH1_DCOSCALEI)
|
|
X(CH1_DCOSTARTVAL)
|
|
X(CH1_DCOSTEP)
|
|
X(CH1_DEC_BYPASS)
|
|
X(CH1_ENABLE_CG_ALIGN)
|
|
X(CH1_ENC_BYPASS)
|
|
X(CH1_FF_RX_F_CLK_DIS)
|
|
X(CH1_FF_RX_H_CLK_EN)
|
|
X(CH1_FF_TX_F_CLK_DIS)
|
|
X(CH1_FF_TX_H_CLK_EN)
|
|
X(CH1_GE_AN_ENABLE)
|
|
X(CH1_INVERT_RX)
|
|
X(CH1_INVERT_TX)
|
|
X(CH1_LDR_CORE2TX_SEL)
|
|
X(CH1_LDR_RX2CORE_SEL)
|
|
X(CH1_LEQ_OFFSET_SEL)
|
|
X(CH1_LEQ_OFFSET_TRIM)
|
|
X(CH1_LSM_DISABLE)
|
|
X(CH1_MATCH_2_ENABLE)
|
|
X(CH1_MATCH_4_ENABLE)
|
|
X(CH1_MIN_IPG_CNT)
|
|
X(CH1_PCIE_EI_EN)
|
|
X(CH1_PCIE_MODE)
|
|
X(CH1_PCS_DET_TIME_SEL)
|
|
X(CH1_PDEN_SEL)
|
|
X(CH1_PRBS_ENABLE)
|
|
X(CH1_PRBS_LOCK)
|
|
X(CH1_PRBS_SELECTION)
|
|
X(CH1_RATE_MODE_RX)
|
|
X(CH1_RATE_MODE_TX)
|
|
X(CH1_RCV_DCC_EN)
|
|
X(CH1_REG_BAND_OFFSET)
|
|
X(CH1_REG_BAND_SEL)
|
|
X(CH1_REG_IDAC_EN)
|
|
X(CH1_REG_IDAC_SEL)
|
|
X(CH1_REQ_EN)
|
|
X(CH1_REQ_LVL_SET)
|
|
X(CH1_RIO_MODE)
|
|
X(CH1_RLOS_SEL)
|
|
X(CH1_RPWDNB)
|
|
X(CH1_RTERM_RX)
|
|
X(CH1_RTERM_TX)
|
|
X(CH1_RXIN_CM)
|
|
X(CH1_RXTERM_CM)
|
|
X(CH1_RX_DCO_CK_DIV)
|
|
X(CH1_RX_DIV11_SEL)
|
|
X(CH1_RX_GEAR_BYPASS)
|
|
X(CH1_RX_GEAR_MODE)
|
|
X(CH1_RX_LOS_CEQ)
|
|
X(CH1_RX_LOS_EN)
|
|
X(CH1_RX_LOS_HYST_EN)
|
|
X(CH1_RX_LOS_LVL)
|
|
X(CH1_RX_RATE_SEL)
|
|
X(CH1_RX_SB_BYPASS)
|
|
X(CH1_SB_BYPASS)
|
|
X(CH1_SEL_SD_RX_CLK)
|
|
X(CH1_TDRV_DAT_SEL)
|
|
X(CH1_TDRV_POST_EN)
|
|
X(CH1_TDRV_PRE_EN)
|
|
X(CH1_TDRV_SLICE0_CUR)
|
|
X(CH1_TDRV_SLICE0_SEL)
|
|
X(CH1_TDRV_SLICE1_CUR)
|
|
X(CH1_TDRV_SLICE1_SEL)
|
|
X(CH1_TDRV_SLICE2_CUR)
|
|
X(CH1_TDRV_SLICE2_SEL)
|
|
X(CH1_TDRV_SLICE3_CUR)
|
|
X(CH1_TDRV_SLICE3_SEL)
|
|
X(CH1_TDRV_SLICE4_CUR)
|
|
X(CH1_TDRV_SLICE4_SEL)
|
|
X(CH1_TDRV_SLICE5_CUR)
|
|
X(CH1_TDRV_SLICE5_SEL)
|
|
X(CH1_TPWDNB)
|
|
X(CH1_TX_CM_SEL)
|
|
X(CH1_TX_DIV11_SEL)
|
|
X(CH1_TX_GEAR_BYPASS)
|
|
X(CH1_TX_GEAR_MODE)
|
|
X(CH1_TX_POST_SIGN)
|
|
X(CH1_TX_PRE_SIGN)
|
|
X(CH1_UC_MODE)
|
|
X(CH1_UDF_COMMA_A)
|
|
X(CH1_UDF_COMMA_B)
|
|
X(CH1_UDF_COMMA_MASK)
|
|
X(CH1_WA_BYPASS)
|
|
X(CH1_WA_MODE)
|
|
X(CIN)
|
|
X(CLAMP)
|
|
X(CLK0_DIV)
|
|
X(CLK1_DIV)
|
|
X(CLK2_DIV)
|
|
X(CLK3_DIV)
|
|
X(CLKAMUX)
|
|
X(CLKBMUX)
|
|
X(CLKFB_DIV)
|
|
X(CLKIMUX)
|
|
X(CLKI_DIV)
|
|
X(CLKOMUX)
|
|
X(CLKOP_DIV)
|
|
X(CLKOP_ENABLE)
|
|
X(CLKOP_TRIM_DELAY)
|
|
X(CLKOP_TRIM_POL)
|
|
X(CLKOS2_DIV)
|
|
X(CLKOS2_ENABLE)
|
|
X(CLKOS3_DIV)
|
|
X(CLKOS3_ENABLE)
|
|
X(CLKOS_DIV)
|
|
X(CLKOS_ENABLE)
|
|
X(CLKOS_TRIM_DELAY)
|
|
X(CLKOS_TRIM_POL)
|
|
X(CLKR)
|
|
X(CLKW)
|
|
X(COUT)
|
|
X(CSDECODE_A)
|
|
X(CSDECODE_B)
|
|
X(D)
|
|
X(D2)
|
|
X(D3)
|
|
X(D4)
|
|
X(D5)
|
|
X(D6)
|
|
X(DATAMUX_MDDR)
|
|
X(DATAMUX_ODDR)
|
|
X(DATAMUX_OREG)
|
|
X(DATA_WIDTH_A)
|
|
X(DATA_WIDTH_B)
|
|
X(DATA_WIDTH_W)
|
|
X(DCSMODE)
|
|
X(DDRDLLA)
|
|
X(DELAYF)
|
|
X(DELAYG)
|
|
X(DEL_MODE)
|
|
X(DEL_VALUE)
|
|
X(DIFFRESISTOR)
|
|
X(DIR)
|
|
X(DIV)
|
|
X(DPHASE_SOURCE)
|
|
X(DQS_LI_DEL_ADJ)
|
|
X(DQS_LI_DEL_VAL)
|
|
X(DQS_LO_DEL_ADJ)
|
|
X(DQS_LO_DEL_VAL)
|
|
X(DRIVE)
|
|
X(D_BITCLK_FROM_ND_EN)
|
|
X(D_BITCLK_LOCAL_EN)
|
|
X(D_BITCLK_ND_EN)
|
|
X(D_BUS8BIT_SEL)
|
|
X(D_CDR_LOL_SET)
|
|
X(D_CMUSETBIASI)
|
|
X(D_CMUSETI4CPP)
|
|
X(D_CMUSETI4CPZ)
|
|
X(D_CMUSETI4VCO)
|
|
X(D_CMUSETICP4P)
|
|
X(D_CMUSETICP4Z)
|
|
X(D_CMUSETINITVCT)
|
|
X(D_CMUSETISCL4VCO)
|
|
X(D_CMUSETP1GM)
|
|
X(D_CMUSETP2AGM)
|
|
X(D_CMUSETZGM)
|
|
X(D_DCO_CALIB_TIME_SEL)
|
|
X(D_HIGH_MARK)
|
|
X(D_IB_PWDNB)
|
|
X(D_ISETLOS)
|
|
X(D_LOW_MARK)
|
|
X(D_MACROPDB)
|
|
X(D_PD_ISET)
|
|
X(D_PLL_LOL_SET)
|
|
X(D_REFCK_MODE)
|
|
X(D_REQ_ISET)
|
|
X(D_RG_EN)
|
|
X(D_RG_SET)
|
|
X(D_SETICONST_AUX)
|
|
X(D_SETICONST_CH)
|
|
X(D_SETIRPOLY_AUX)
|
|
X(D_SETIRPOLY_CH)
|
|
X(D_SETPLLRC)
|
|
X(D_SYNC_LOCAL_EN)
|
|
X(D_SYNC_ND_EN)
|
|
X(D_TXPLL_PWDNB)
|
|
X(D_TX_VCO_CK_DIV)
|
|
X(D_XGE_MODE)
|
|
X(E)
|
|
X(ECP5_IS_GLOBAL)
|
|
X(ER1)
|
|
X(ER2)
|
|
X(FEEDBK_PATH)
|
|
X(FORCE_MAX_DELAY)
|
|
X(FORCE_ZERO_BARREL_SHIFT)
|
|
X(FREQ_LOCK_ACCURACY)
|
|
X(GND)
|
|
X(HYSTERESIS)
|
|
X(ICP_CURRENT)
|
|
X(IDDR71B)
|
|
X(IDDRX1F)
|
|
X(IDDRX2DQA)
|
|
X(IDDRX2F)
|
|
X(INIT)
|
|
X(INIT0)
|
|
X(INIT1)
|
|
X(INITVAL)
|
|
X(INJECT1_0)
|
|
X(INJECT1_1)
|
|
X(INTFB_WAKE)
|
|
X(INT_LOCK_STICKY)
|
|
X(INV)
|
|
X(IOLTOMUX)
|
|
X(IO_TYPE)
|
|
X(KVCO)
|
|
X(L6MUX21)
|
|
X(LEGACY)
|
|
X(LOC)
|
|
X(LPF_CAPACITOR)
|
|
X(LPF_RESISTOR)
|
|
X(LSRIMUX)
|
|
X(LSRMODE)
|
|
X(LSROMUX)
|
|
X(LUT0_INITVAL)
|
|
X(LUT1_INITVAL)
|
|
X(LUT4)
|
|
X(M)
|
|
X(MASK01)
|
|
X(MASKPAT)
|
|
X(MASKPAT_SOURCE)
|
|
X(MCPAT)
|
|
X(MCPAT_SOURCE)
|
|
X(MFG1_TEST)
|
|
X(MFG2_TEST)
|
|
X(MFG_ENABLE_FILTEROPAMP)
|
|
X(MFG_EN_UP)
|
|
X(MFG_FLOAT_ICP)
|
|
X(MFG_FORCE_VFILTER)
|
|
X(MFG_GMCREF_SEL)
|
|
X(MFG_GMC_GAIN)
|
|
X(MFG_GMC_PRESET)
|
|
X(MFG_GMC_RESET)
|
|
X(MFG_GMC_TEST)
|
|
X(MFG_ICP_TEST)
|
|
X(MFG_LF_PRESET)
|
|
X(MFG_LF_RESET)
|
|
X(MFG_LF_RESGRND)
|
|
X(MODE)
|
|
X(MULT_BYPASS)
|
|
X(OCEAMUX)
|
|
X(OCEBMUX)
|
|
X(OCER)
|
|
X(ODDR71B)
|
|
X(ODDRX1F)
|
|
X(ODDRX2DQA)
|
|
X(ODDRX2DQSB)
|
|
X(ODDRX2F)
|
|
X(OPENDRAIN)
|
|
X(OSHX2A)
|
|
X(OUTDIVIDER_MUXA)
|
|
X(OUTDIVIDER_MUXB)
|
|
X(OUTDIVIDER_MUXC)
|
|
X(OUTDIVIDER_MUXD)
|
|
X(PDPW16KD)
|
|
X(PFUMX)
|
|
X(PLLRST_ENA)
|
|
X(PLL_LOCK_MODE)
|
|
X(PULLMODE)
|
|
X(Q)
|
|
X(Q2)
|
|
X(Q3)
|
|
X(Q4)
|
|
X(Q5)
|
|
X(Q6)
|
|
X(QWL)
|
|
X(REFCK_DCBIAS_EN)
|
|
X(REFCK_PWDNB)
|
|
X(REFCK_RTERM)
|
|
X(REFIN_RESET)
|
|
X(REG0_LSRMODE)
|
|
X(REG0_REGSET)
|
|
X(REG0_SD)
|
|
X(REG1_LSRMODE)
|
|
X(REG1_REGSET)
|
|
X(REG1_SD)
|
|
X(REGMODE)
|
|
X(REGMODE_A)
|
|
X(REGMODE_B)
|
|
X(REGSET)
|
|
X(REG_FLAG_CLK)
|
|
X(REG_INPUTA_CE)
|
|
X(REG_INPUTA_CLK)
|
|
X(REG_INPUTA_RST)
|
|
X(REG_INPUTB_CE)
|
|
X(REG_INPUTB_CLK)
|
|
X(REG_INPUTB_RST)
|
|
X(REG_INPUTC0_CLK)
|
|
X(REG_INPUTC1_CLK)
|
|
X(REG_INPUTC_CLK)
|
|
X(REG_OPCODEIN_0_CE)
|
|
X(REG_OPCODEIN_0_CLK)
|
|
X(REG_OPCODEIN_0_RST)
|
|
X(REG_OPCODEIN_1_CE)
|
|
X(REG_OPCODEIN_1_CLK)
|
|
X(REG_OPCODEIN_1_RST)
|
|
X(REG_OPCODEOP0_0_CE)
|
|
X(REG_OPCODEOP0_0_CLK)
|
|
X(REG_OPCODEOP0_0_RST)
|
|
X(REG_OPCODEOP0_1_CE)
|
|
X(REG_OPCODEOP0_1_CLK)
|
|
X(REG_OPCODEOP0_1_RST)
|
|
X(REG_OPCODEOP1_0_CLK)
|
|
X(REG_OPCODEOP1_1_CLK)
|
|
X(REG_OUTPUT0_CLK)
|
|
X(REG_OUTPUT1_CLK)
|
|
X(REG_OUTPUT_CLK)
|
|
X(REG_OUTPUT_RST)
|
|
X(REG_PIPELINE_CE)
|
|
X(REG_PIPELINE_CLK)
|
|
X(REG_PIPELINE_RST)
|
|
X(RESETMODE)
|
|
X(RNDPAT)
|
|
X(RSTAMUX)
|
|
X(RSTBMUX)
|
|
X(S0)
|
|
X(S1)
|
|
X(SD)
|
|
X(SGSR)
|
|
X(SLEWRATE)
|
|
X(SOURCEB_MODE)
|
|
X(STDBY_ENABLE)
|
|
X(SYNCMODE)
|
|
X(SYNC_ENABLE)
|
|
X(T0)
|
|
X(T1)
|
|
X(TERMINATION)
|
|
X(TILE_WIRE_ID)
|
|
X(TRELLIS_DPR16X4)
|
|
X(TRELLIS_FF)
|
|
X(TRIMUX_TSREG)
|
|
X(TSHX2DQA)
|
|
X(TSHX2DQSA)
|
|
X(USRMCLKI)
|
|
X(USRMCLKO)
|
|
X(USRMCLKTS)
|
|
X(VCC)
|
|
X(WCKMUX)
|
|
X(WEAMUX)
|
|
X(WEBMUX)
|
|
X(WID)
|
|
X(WREMUX)
|
|
X(WRITEMODE_A)
|
|
X(WRITEMODE_B)
|
|
X(Y)
|
|
X(ioff_dir)
|
|
X(lfe5u_12f)
|
|
X(lfe5u_25f)
|
|
X(lfe5u_45f)
|
|
X(lfe5u_85f)
|
|
X(lfe5um5g_25f)
|
|
X(lfe5um5g_45f)
|
|
X(lfe5um5g_85f)
|
|
X(lfe5um_25f)
|
|
X(lfe5um_45f)
|
|
X(lfe5um_85f)
|
|
X(noglobal)
|
|
X(pack)
|
|
X(place)
|
|
X(placer)
|
|
X(route)
|
|
X(router)
|
|
X(syn_useioff)
|
|
|
|
X(TRELLIS_COMB)
|
|
X(TRELLIS_RAMW)
|
|
X(TRELLIS_COMB_CARRY0)
|
|
X(TRELLIS_COMB_CARRY1)
|
|
|
|
X(WD)
|
|
X(OFX)
|
|
X(F)
|
|
X(CCU2_INJECT1)
|