33 lines
607 B
Verilog
33 lines
607 B
Verilog
module blinky (
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input clki,
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output led0,
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output led1,
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output led2,
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output led3
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);
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BUFGCTRL clk_gb (
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.I0(clki),
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.CE0(1'b1),
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.CE1(1'b0),
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.S0(1'b1),
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.S1(1'b0),
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.IGNORE0(1'b0),
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.IGNORE1(1'b0),
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.O(clk)
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);
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localparam BITS = 4;
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localparam LOG2DELAY = 21;
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reg [BITS+LOG2DELAY-1:0] counter = 0;
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reg [BITS-1:0] outcnt;
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always @(posedge clk) begin
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counter <= counter + 1;
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outcnt <= counter >> LOG2DELAY;
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end
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assign {led0, led1, led2, led3} = outcnt ^ (outcnt >> 1);
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endmodule
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