
* ng-ultra: new architecture * Implementation as in D2 deliverable * Support for nxdesignsuite-24.0.0.0-20240429T102300 * Save memory by directly outputing json * Add support for bidirectional IOs * cleanup * Create BFRs properly * Add IOM insertion * Cleanup * Block certain pips depending of DDFR mode * Add LUT bypass to improve routability * Add bypass for CSC mode of GCK * Fix IOM case * Initial memory support * Better RF/XRF handling * fix * RF placement and legalization * Disconnect non available ports for NX_RAM * cleanup * Add RFB/RAM context support for latest release * Remove ports that must not be used * Proper port used only on RFB * Add structure for clock sinks * Use cell type where applicable * Add clock sinks for other cell types * Validation check fixes * Commented too restrictive placement * Added more crossbar wire type * Hande IO termination input * Fail early due to NX tools limitation for now * Validations and fixes for RAM I/Os * Fix for latest version of tools * Use ctx->idf where applicable * warn if RAM ports are not actually used * Fix IOM packing * Fix CY packing * Change how constants are handled on CY * Post placement optimization for CY * Address comments for PR * pack and export GCK, WFG and PLL * Cover more global routing cases * Constraing to location if provided * Place at LOC * Pack and export DSP * wip * wip * notes * wip * wip * Validate DSPs * DSP cascading * Check mandatory parameters for DSP * existing gck * wip * export all the rest for bitstream * CDC packing * add more sinks * place FIFO * map rest of FIFO ports * enable pll by default * cleanup * Initial XLUT support * Fix statistics * Properly duplicate GCKs * RRSTO and WRSTO are not used on XFIFO * Fix for latest version of JSON format * Implement GCK limitations * cleanup * cleanup * Add more signals and use lowskew name * cleanup code a bit * Fix wfb * detect cascaded GCKs * Handle DFR * Route dfr clock properly * Cleanup * Cleanup bitstream code * Review issues addressed * Move helper routines * Expose private members for unit tests * cleanup * remove scale factor * make all location helper arrays static * Addressed review comments * Support post-routing CSC and SCC * Support NX_BFF * Place CSS and SCC only on allowed locations * Support latest Impulse * ng_ultra: Expand bounding box further for left-edge IO Signed-off-by: gatecat <gatecat@ds0.me> * Export all IO parameters in bitstream * Handle new CSV order or parameters and additional validation * Add some more undocumented values for CSV * Support for old and new CSV formats * Initial DDFR support * Display warning message once per file * Address review issues * Fix crash on memory access * Make boundbox fit NG-Ultra internal design * Update attributes after dff rewrite * Implement basic NG-Ultra LUT-DFF unit tests * Always use first seen xbar input Signed-off-by: gatecat <gatecat@ds0.me> * Simplified crossbar pip detection * Change order to prevent issues with some unconnected constants * Pack LUT and multiple DFF in stripe * Place DFF chains * Improve large DFF chains * Rename to pack_dff_chains * Better use XLUTs when possible * pack output DFF together with XLUT * option to disable XLUT optimiziations * Make more optimizations optional * fix to use pre-increment * GCK for lowskew signals * Bugfix for nets that are not part of lowskew network * Fix bitstream export for PLL cell * Remove separate route lowskew * Allow WFG mode 2 * Merge inverter into GCK * Add CSC per TILE when needed * Improve reusage of existing cell for CSC * Take preferred CSC * Cleanup * When in place CSC size not important * Cleanup * Reset and Load restriction * make csc optimisation optional * Proper count for IO resources * Detect when there is no next cell for DSP chain * Do not incorporate loops in XLUT * Check if output exists * Update copyright for delivery * Make building NG-Ultra chip database optional, follow filename convention * Ported drawing code to new API * Update expandBoundingBox for NG-Ultra * Copyright and license update * Add README information * cleanup and constids * Using ctx->idf where applicable * remove if_using_basecluster * refactor extra data usage * refactor to use create_cell_ptr only * optimized getCSC * optimize critical path a bit * clangformat * disable clangformat where applicable --------- Signed-off-by: gatecat <gatecat@ds0.me> Co-authored-by: Lofty <dan.ravensloft@gmail.com> Co-authored-by: gatecat <gatecat@ds0.me>
266 lines
5.4 KiB
C
266 lines
5.4 KiB
C
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2024 The Project Beyond Authors.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef NGULTRA_EXTRA_DATA_H
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#define NGULTRA_EXTRA_DATA_H
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#include "nextpnr.h"
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NEXTPNR_NAMESPACE_BEGIN
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NPNR_PACKED_STRUCT(struct NGUltraTileInstExtraDataPOD {
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int32_t name;
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uint8_t lobe;
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uint8_t tile_type;
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uint16_t dummy2;
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});
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NPNR_PACKED_STRUCT(struct NGUltraPipExtraDataPOD {
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int32_t name;
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uint16_t type;
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uint8_t input;
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uint8_t output;
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});
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NPNR_PACKED_STRUCT(struct NGUltraBelExtraDataPOD { int32_t flags; });
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struct GckConfig
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{
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explicit GckConfig(BelId belid)
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{
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bel = belid;
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si1 = IdString();
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si2 = IdString();
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used = false;
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}
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BelId bel;
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IdString si1;
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IdString si2;
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bool used;
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};
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enum TILETypeZ
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{
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BEL_LUT_Z = 0,
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BEL_LUT_MAX_Z = 31,
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BEL_CY_Z = 32,
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BEL_XLUT_Z = BEL_CY_Z + 4,
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BEL_RF_Z = BEL_XLUT_Z + 8,
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BEL_XRF_Z = BEL_RF_Z + 2,
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BEL_FIFO_Z = BEL_XRF_Z + 1,
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BEL_XFIFO_Z = BEL_FIFO_Z + 2,
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BEL_CDC_Z = BEL_XFIFO_Z + 1,
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BEL_XCDC_Z = BEL_CDC_Z + 2
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};
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enum ClusterPlacement
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{
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PLACE_CY_CHAIN = 1024,
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PLACE_CY_FE1,
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PLACE_CY_FE2,
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PLACE_CY_FE3,
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PLACE_CY_FE4,
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PLACE_XLUT_FE1,
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PLACE_XLUT_FE2,
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PLACE_XLUT_FE3,
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PLACE_XLUT_FE4,
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PLACE_XRF_I1,
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PLACE_XRF_I2,
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PLACE_XRF_I3,
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PLACE_XRF_I4,
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PLACE_XRF_I5,
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PLACE_XRF_I6,
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PLACE_XRF_I7,
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PLACE_XRF_I8,
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PLACE_XRF_I9,
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PLACE_XRF_I10,
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PLACE_XRF_I11,
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PLACE_XRF_I12,
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PLACE_XRF_I13,
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PLACE_XRF_I14,
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PLACE_XRF_I15,
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PLACE_XRF_I16,
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PLACE_XRF_I17,
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PLACE_XRF_I18,
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PLACE_XRF_I19,
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PLACE_XRF_I20,
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PLACE_XRF_I21,
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PLACE_XRF_I22,
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PLACE_XRF_I23,
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PLACE_XRF_I24,
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PLACE_XRF_I25,
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PLACE_XRF_I26,
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PLACE_XRF_I27,
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PLACE_XRF_I28,
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PLACE_XRF_I29,
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PLACE_XRF_I30,
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PLACE_XRF_I31,
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PLACE_XRF_I32,
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PLACE_XRF_I33,
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PLACE_XRF_I34,
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PLACE_XRF_I35,
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PLACE_XRF_I36,
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PLACE_XRF_RA1,
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PLACE_XRF_RA2,
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PLACE_XRF_RA3,
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PLACE_XRF_RA4,
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PLACE_XRF_RA5,
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PLACE_XRF_RA6,
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PLACE_XRF_RA7,
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PLACE_XRF_RA8,
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PLACE_XRF_RA9,
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PLACE_XRF_RA10,
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PLACE_XRF_WA1,
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PLACE_XRF_WA2,
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PLACE_XRF_WA3,
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PLACE_XRF_WA4,
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PLACE_XRF_WA5,
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PLACE_XRF_WA6,
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PLACE_XRF_WE,
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PLACE_XRF_WEA,
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PLACE_DSP_CHAIN,
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PLACE_CDC_AI1,
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PLACE_CDC_AI2,
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PLACE_CDC_AI3,
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PLACE_CDC_AI4,
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PLACE_CDC_AI5,
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PLACE_CDC_AI6,
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PLACE_CDC_BI1,
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PLACE_CDC_BI2,
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PLACE_CDC_BI3,
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PLACE_CDC_BI4,
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PLACE_CDC_BI5,
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PLACE_CDC_BI6,
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PLACE_CDC_ASRSTI,
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PLACE_CDC_ADRSTI,
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PLACE_CDC_BSRSTI,
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PLACE_CDC_BDRSTI,
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PLACE_CDC_CI1,
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PLACE_CDC_CI2,
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PLACE_CDC_CI3,
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PLACE_CDC_CI4,
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PLACE_CDC_CI5,
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PLACE_CDC_CI6,
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PLACE_CDC_DI1,
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PLACE_CDC_DI2,
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PLACE_CDC_DI3,
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PLACE_CDC_DI4,
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PLACE_CDC_DI5,
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PLACE_CDC_DI6,
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PLACE_CDC_CSRSTI,
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PLACE_CDC_CDRSTI,
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PLACE_CDC_DSRSTI,
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PLACE_CDC_DDRSTI,
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PLACE_FIFO_I1,
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PLACE_FIFO_I2,
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PLACE_FIFO_I3,
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PLACE_FIFO_I4,
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PLACE_FIFO_I5,
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PLACE_FIFO_I6,
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PLACE_FIFO_I7,
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PLACE_FIFO_I8,
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PLACE_FIFO_I9,
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PLACE_FIFO_I10,
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PLACE_FIFO_I11,
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PLACE_FIFO_I12,
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PLACE_FIFO_I13,
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PLACE_FIFO_I14,
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PLACE_FIFO_I15,
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PLACE_FIFO_I16,
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PLACE_FIFO_I17,
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PLACE_FIFO_I18,
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PLACE_FIFO_I19,
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PLACE_FIFO_I20,
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PLACE_FIFO_I21,
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PLACE_FIFO_I22,
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PLACE_FIFO_I23,
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PLACE_FIFO_I24,
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PLACE_FIFO_I25,
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PLACE_FIFO_I26,
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PLACE_FIFO_I27,
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PLACE_FIFO_I28,
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PLACE_FIFO_I29,
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PLACE_FIFO_I30,
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PLACE_FIFO_I31,
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PLACE_FIFO_I32,
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PLACE_FIFO_I33,
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PLACE_FIFO_I34,
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PLACE_FIFO_I35,
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PLACE_FIFO_I36,
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PLACE_FIFO_RAI1,
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PLACE_FIFO_RAI2,
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PLACE_FIFO_RAI3,
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PLACE_FIFO_RAI4,
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PLACE_FIFO_RAI5,
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PLACE_FIFO_RAI6,
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PLACE_FIFO_RAI7,
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PLACE_FIFO_WAI1,
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PLACE_FIFO_WAI2,
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PLACE_FIFO_WAI3,
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PLACE_FIFO_WAI4,
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PLACE_FIFO_WAI5,
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PLACE_FIFO_WAI6,
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PLACE_FIFO_WAI7,
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PLACE_FIFO_WE,
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PLACE_FIFO_WEA,
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PLACE_FIFO_WRSTI1,
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PLACE_FIFO_RRSTI1,
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PLACE_FIFO_WRSTI2,
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PLACE_FIFO_RRSTI2,
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PLACE_FIFO_WRSTI3,
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PLACE_FIFO_RRSTI3,
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PLACE_FIFO_WRSTI4,
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PLACE_FIFO_RRSTI4,
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PLACE_FIFO_WEQ1,
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PLACE_FIFO_REQ1,
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PLACE_FIFO_WEQ2,
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PLACE_FIFO_REQ2,
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PLACE_LUT_CHAIN,
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PLACE_DFF_CHAIN,
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};
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enum PipExtra
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{
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PIP_EXTRA_CROSSBAR = 1,
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PIP_EXTRA_MUX = 2,
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PIP_EXTRA_BYPASS = 3,
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PIP_EXTRA_LUT_PERMUTATION = 4,
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PIP_EXTRA_INTERCONNECT = 5,
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PIP_EXTRA_VIRTUAL = 6,
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};
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enum BelExtra
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{
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BEL_EXTRA_FE_CSC = 1,
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BEL_EXTRA_FE_SCC = 2,
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};
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enum TileTypeExtra
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{
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TILE_EXTRA_FABRIC = 0,
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TILE_EXTRA_TUBE = 1,
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TILE_EXTRA_SOC = 2,
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TILE_EXTRA_RING = 3,
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TILE_EXTRA_FENCE = 4
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};
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NEXTPNR_NAMESPACE_END
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#endif
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