69 lines
1.1 KiB
Verilog
69 lines
1.1 KiB
Verilog
module \$_DFF_P_ (input D, C, output Q);
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TRELLIS_SLICE #(
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.MODE("LOGIC"),
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.CLKMUX("CLK"),
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.CEMUX("1"),
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.REG0_SD("0"),
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.REG0_REGSET("RESET"),
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.SRMODE("LSR_OVER_CE"),
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.GSR("DISABLED")
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) _TECHMAP_REPLACE_ (
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.CLK(C),
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.M0(D),
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.Q0(Q)
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);
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endmodule
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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input [WIDTH-1:0] A;
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output Y;
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generate
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if (WIDTH == 1) begin
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TRELLIS_SLICE #(
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.MODE("LOGIC"),
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.LUT0_INITVAL({8{LUT[1:0]}})
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) _TECHMAP_REPLACE_ (
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.A0(A[0]),
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.F0(Y)
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);
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end
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if (WIDTH == 2) begin
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TRELLIS_SLICE #(
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.MODE("LOGIC"),
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.LUT0_INITVAL({4{LUT[3:0]}})
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) _TECHMAP_REPLACE_ (
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.A0(A[0]),
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.B0(A[1]),
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.F0(Y)
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);
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end
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if (WIDTH == 3) begin
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TRELLIS_SLICE #(
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.MODE("LOGIC"),
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.LUT0_INITVAL({2{LUT[7:0]}})
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) _TECHMAP_REPLACE_ (
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.A0(A[0]),
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.B0(A[1]),
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.C0(A[2]),
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.F0(Y)
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);
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end
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if (WIDTH == 4) begin
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TRELLIS_SLICE #(
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.MODE("LOGIC"),
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.LUT0_INITVAL(LUT)
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) _TECHMAP_REPLACE_ (
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.A0(A[0]),
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.B0(A[1]),
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.C0(A[2]),
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.D0(A[3]),
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.F0(Y)
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);
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end
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endgenerate
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endmodule
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