19 lines
707 B
Verilog
19 lines
707 B
Verilog
module top(input a_pin, output led_pin, output led2_pin, output gpio0_pin);
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wire a;
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wire led, led2;
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wire gpio0;
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(* BEL="X4/Y71/PIOA" *) (* IO_TYPE="LVCMOS33" *)
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TRELLIS_IO #(.DIR("INPUT")) a_buf (.B(a_pin), .O(a));
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(* BEL="X0/Y23/PIOC" *) (* IO_TYPE="LVCMOS33" *)
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TRELLIS_IO #(.DIR("OUTPUT")) led_buf (.B(led_pin), .I(led));
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(* BEL="X0/Y26/PIOA" *) (* IO_TYPE="LVCMOS33" *)
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TRELLIS_IO #(.DIR("OUTPUT")) led2_buf (.B(led2_pin), .I(led2));
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(* BEL="X0/Y62/PIOD" *) (* IO_TYPE="LVCMOS33" *)
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TRELLIS_IO #(.DIR("OUTPUT")) gpio0_buf (.B(gpio0_pin), .I(gpio0));
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assign led = a;
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assign led2 = !a;
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TRELLIS_SLICE #(.MODE("LOGIC"), .LUT0_INITVAL(16'hFFFF)) vcc (.F0(gpio0));
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endmodule
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