91b0c4f90a
The OCE signal in the SP(X)9B primitive is intended to control the
built-in output register. The documentation states that this port is
invalid when READ_MODE=0 is used. However, it has been experimentally
established that you cannot simply apply VCC or GND to it and forget it
- the discrepancy between the signal on this port and the signal on the
CE port leads to both skipping data reading and unnecessary reading
after CE has switched to 0.
Here we force these ports to be connected to the network, except in the
case where the user controls the OCE signal using non-constant signals.
Also:
* All PIPs for clock spines are made inaccessible to the common router
- in general, using these routes for signals that have not been
processed by a special globals router is fraught with effects that
are difficult to detect.
* The INV primitive has been added purely to speed up development -
this primitive is not generated by Yosys, but is almost always
present in vendor output files.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
67 lines
1.9 KiB
C++
67 lines
1.9 KiB
C++
#ifndef GOWIN_UTILS_H
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#define GOWIN_UTILS_H
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#include "idstringlist.h"
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#include "nextpnr_namespaces.h"
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#include "nextpnr_types.h"
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NEXTPNR_NAMESPACE_BEGIN
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namespace BelFlags {
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static constexpr uint32_t FLAG_SIMPLE_IO = 0x100;
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}
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struct GowinUtils
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{
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Context *ctx;
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GowinUtils() {}
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void init(Context *ctx) { this->ctx = ctx; }
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// tile
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IdString get_tile_class(int x, int y);
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Loc get_tile_io16_offs(int x, int y);
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// pin functions: GCLKT_4, SSPI_CS, READY etc
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IdStringList get_pin_funcs(BelId bel);
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// Bels and pips
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bool is_simple_io_bel(BelId bel);
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Loc get_pair_iologic_bel(Loc loc);
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BelId get_io_bel_from_iologic(BelId bel);
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bool is_diff_io_supported(IdString type);
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bool have_bottom_io_cnds(void);
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IdString get_bottom_io_wire_a_net(int8_t condition);
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IdString get_bottom_io_wire_b_net(int8_t condition);
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// wires
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inline bool is_wire_type_default(IdString wire_type) { return wire_type == IdString(); }
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// If wire is an important part of the global network (like SPINExx)
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inline bool is_global_wire(WireId wire) const
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{
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return ctx->getWireName(wire)[1].in(
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id_SPINE0, id_SPINE1, id_SPINE2, id_SPINE3, id_SPINE4, id_SPINE5, id_SPINE6, id_SPINE7, id_SPINE8,
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id_SPINE9, id_SPINE10, id_SPINE11, id_SPINE12, id_SPINE13, id_SPINE14, id_SPINE15, id_SPINE16,
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id_SPINE17, id_SPINE18, id_SPINE19, id_SPINE20, id_SPINE21, id_SPINE22, id_SPINE23, id_SPINE24,
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id_SPINE25, id_SPINE26, id_SPINE27, id_SPINE28, id_SPINE29, id_SPINE30, id_SPINE31);
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}
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// pips
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inline bool is_global_pip(PipId pip) const
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{
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return is_global_wire(ctx->getPipSrcWire(pip)) || is_global_wire(ctx->getPipDstWire(pip));
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}
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// chip dependent
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bool have_SP32(void);
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// make cell but do not include it in the list of chip cells.
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std::unique_ptr<CellInfo> create_cell(IdString name, IdString type);
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};
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NEXTPNR_NAMESPACE_END
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#endif
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