150 lines
6.1 KiB
C++
150 lines
6.1 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 David Shah <david@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "bitstream.h"
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// From Project Trellis
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#include "BitDatabase.hpp"
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#include "Bitstream.hpp"
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#include "Chip.hpp"
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#include "ChipConfig.hpp"
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#include "Tile.hpp"
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#include "TileConfig.hpp"
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#include <fstream>
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#include <streambuf>
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#include "log.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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// Convert an absolute wire name to a relative Trellis one
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static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire)
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{
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std::string basename = ctx->locInfo(wire)->wire_data[wire.index].name.get();
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std::string prefix2 = basename.substr(0, 2);
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if (prefix2 == "G_" || prefix2 == "L_" || prefix2 == "R_")
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return basename;
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if (loc == wire.location)
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return basename;
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std::string rel_prefix;
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if (wire.location.y < loc.y)
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rel_prefix += "N" + to_string(loc.y - wire.location.y);
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if (wire.location.y > loc.y)
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rel_prefix += "S" + to_string(wire.location.y - loc.y);
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if (wire.location.x > loc.x)
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rel_prefix += "E" + to_string(wire.location.x - loc.x);
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if (wire.location.x < loc.x)
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rel_prefix += "W" + to_string(loc.x - wire.location.x);
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return rel_prefix + "_" + basename;
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}
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static std::vector<bool> int_to_bitvector(int val, int size)
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{
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std::vector<bool> bv;
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for (int i = 0; i < size; i++) {
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bv.push_back((val & (1 << i)) != 0);
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}
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return bv;
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}
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void write_bitstream(Context *ctx, std::string base_config_file, std::string text_config_file,
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std::string bitstream_file)
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{
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Trellis::Chip empty_chip(ctx->getChipName());
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Trellis::ChipConfig cc;
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if (!base_config_file.empty()) {
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std::ifstream config_file(base_config_file);
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if (!config_file) {
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log_error("failed to open base config file '%s'\n", base_config_file.c_str());
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}
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std::string str((std::istreambuf_iterator<char>(config_file)), std::istreambuf_iterator<char>());
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cc = Trellis::ChipConfig::from_string(str);
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} else {
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cc.chip_name = ctx->getChipName();
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// TODO: .bit metadata
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}
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// Add all set, configurable pips to the config
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for (auto pip : ctx->getPips()) {
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if (ctx->getBoundPipNet(pip) != IdString()) {
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if (ctx->getPipType(pip) == 0) { // ignore fixed pips
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auto tile = empty_chip.get_tile_by_position_and_type(pip.location.y, pip.location.x,
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ctx->getPipTiletype(pip));
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std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip));
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std::string sink = get_trellis_wirename(ctx, pip.location, ctx->getPipDstWire(pip));
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cc.tiles[tile->info.name].add_arc(sink, source);
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}
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}
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}
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// Set all bankref tiles to 3.3V (TODO)
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for (const auto &tile : empty_chip.tiles) {
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std::string type = tile.second->info.type;
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if (type.find("BANKREF") != std::string::npos && type != "BANKREF8") {
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cc.tiles[type].add_enum("BANK.VCCIO", "3V3");
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}
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}
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// Configure slices
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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if (ci->bel == BelId()) {
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log_warning("found unplaced cell '%s' during bitstream gen\n", ci->name.c_str(ctx));
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}
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BelId bel = ci->bel;
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if (ci->type == ctx->id("TRELLIS_SLICE")) {
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auto tile = empty_chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, "PLC2");
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std::string tname = tile->info.name;
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std::string slice = ctx->locInfo(bel)->bel_data[bel.index].name.get();
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int lut0_init = int_or_default(ci->params, ctx->id("LUT0_INITVAL"));
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int lut1_init = int_or_default(ci->params, ctx->id("LUT1_INITVAL"));
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cc.tiles[tname].add_word(slice + ".K0.INIT", int_to_bitvector(lut0_init, 16));
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cc.tiles[tname].add_word(slice + ".K1.INIT", int_to_bitvector(lut1_init, 16));
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cc.tiles[tname].add_enum(slice + ".MODE", str_or_default(ci->params, ctx->id("MODE"), "LOGIC"));
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cc.tiles[tname].add_enum(slice + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "ENABLED"));
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cc.tiles[tname].add_enum(slice + ".REG0.SD", str_or_default(ci->params, ctx->id("REG0_SD"), "0"));
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cc.tiles[tname].add_enum(slice + ".REG1.SD", str_or_default(ci->params, ctx->id("REG1_SD"), "0"));
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cc.tiles[tname].add_enum(slice + ".REG0.REGSET",
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str_or_default(ci->params, ctx->id("REG0_REGSET"), "RESET"));
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cc.tiles[tname].add_enum(slice + ".REG1.REGSET",
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str_or_default(ci->params, ctx->id("REG1_REGSET"), "RESET"));
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cc.tiles[tname].add_enum(slice + ".CEMUX", str_or_default(ci->params, ctx->id("CEMUX"), "1"));
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// TODO: CLKMUX, CEMUX, carry
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} else if (ci->type == ctx->id("TRELLIS_IO")) {
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// TODO: IO config
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} else {
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NPNR_ASSERT_FALSE("unsupported cell type");
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}
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}
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// Configure chip
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Trellis::Chip cfg_chip = cc.to_chip();
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if (!bitstream_file.empty()) {
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Trellis::Bitstream::serialise_chip(cfg_chip).write_bit_py(bitstream_file);
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}
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if (!text_config_file.empty()) {
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std::ofstream out_config(text_config_file);
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out_config << cc.to_string();
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}
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}
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NEXTPNR_NAMESPACE_END
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