59 lines
948 B
Verilog
59 lines
948 B
Verilog
// LUT and DFF are combined to a GENERIC_SLICE
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module LUT #(
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parameter K = 4,
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parameter [2**K-1:0] INIT = 0,
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) (
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input [K-1:0] I,
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output Q
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);
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assign Q = INIT[I];
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endmodule
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module DFF (
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input CLK, D,
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output reg Q
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);
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always @(posedge CLK)
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Q <= D;
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endmodule
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module GENERIC_SLICE #(
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parameter K = 4,
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parameter [2**K-1:0] INIT = 0,
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parameter FF_USED = 1'b0
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) (
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input CLK,
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input [K-1:0] I,
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output Q
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);
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wire lut_q;
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LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(lut_q));
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generate if (FF_USED)
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DFF dff_i(.CLK(CLK), .D(lut_q), .Q(Q));
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else
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assign Q = lut_q;
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endgenerate
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endmodule
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module GENERIC_IOB #(
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parameter INPUT_USED = 1'b0,
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parameter OUTPUT_USED = 1'b0,
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parameter ENABLE_USED = 1'b0
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) (
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inout PAD,
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input I, EN,
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output O
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);
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generate if (OUTPUT_USED && ENABLE_USED)
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assign PAD = EN ? I : 1'bz;
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else if (OUTPUT_USED)
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assign PAD = I;
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endgenerate
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generate if (INPUT_USED)
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assign O = PAD;
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endgenerate
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endmodule |