nextpnr/fpga_interchange/examples/tests/lut_nexus/lut.v
gatecat ecfaae7f9e interchange: Add Nexus LUT test
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-30 16:31:51 +01:00

7 lines
149 B
Verilog

module top;
wire x, y;
(*keep*)
LUT4 lut_0(.A(x), .B(x), .C(x), .D(x), .Z(y));
(*keep*)
LUT4 lut_1(.A(y), .B(y), .C(y), .D(y), .Z(x));
endmodule