204 lines
8.3 KiB
C++
204 lines
8.3 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2021 Lofty <dan.ravensloft@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef NEXTPNR_H
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#error Include "arch.h" via "nextpnr.h" only.
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#endif
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#include "mistral/lib/cyclonev.h"
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NEXTPNR_NAMESPACE_BEGIN
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struct ArchArgs
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{
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std::string device;
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};
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struct Arch : BaseCtx
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{
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ArchArgs args;
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mistral::CycloneV* cyclonev;
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Arch(ArchArgs args);
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std::string getChipName() const { return std::string{"TODO: getChipName"}; }
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IdString archId() const { return id("cyclonev"); }
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ArchArgs archArgs() const { return args; }
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IdString archArgsToId(ArchArgs args) const { return id("TODO: archArgsToId"); }
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// -------------------------------------------------
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int getGridDimX() const { return cyclonev->get_tile_sx(); }
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int getGridDimY() const { return cyclonev->get_tile_sy(); }
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int getTileBelDimZ(int x, int y) const; // arch.cc
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int getTilePipDimZ(int x, int y) const { return 1; }
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// -------------------------------------------------
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BelId getBelByName(IdString name) const; // arch.cc
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IdString getBelName(BelId bel) const; // arch.cc
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uint32_t getBelChecksum(BelId bel) const { return (bel.pos << 16) | bel.z; }
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void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength);
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void unbindBel(BelId bel);
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bool checkBelAvail(BelId bel) const;
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CellInfo *getBoundBelCell(BelId bel) const;
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CellInfo *getConflictingBelCell(BelId bel) const;
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const std::vector<BelId> &getBels() const;
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Loc getBelLocation(BelId bel) const;
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BelId getBelByLocation(Loc loc) const;
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const std::vector<BelId> &getBelsByTile(int x, int y) const;
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bool getBelGlobalBuf(BelId bel) const;
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IdString getBelType(BelId bel) const;
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std::vector<std::pair<IdString, std::string>> getBelAttrs(BelId bel) const;
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WireId getBelPinWire(BelId bel, IdString pin) const;
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PortType getBelPinType(BelId bel, IdString pin) const;
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std::vector<IdString> getBelPins(BelId bel) const;
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bool isBelLocked(BelId bel) const;
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// -------------------------------------------------
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WireId getWireByName(IdString name) const;
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IdString getWireName(WireId wire) const;
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IdString getWireType(WireId wire) const;
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std::vector<std::pair<IdString, std::string>> getWireAttrs(WireId wire) const;
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uint32_t getWireChecksum(WireId wire) const;
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void bindWire(WireId wire, NetInfo *net, PlaceStrength strength);
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void unbindWire(WireId wire);
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bool checkWireAvail(WireId wire) const;
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NetInfo *getBoundWireNet(WireId wire) const;
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WireId getConflictingWireWire(WireId wire) const;
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NetInfo *getConflictingWireNet(WireId wire) const;
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DelayInfo getWireDelay(WireId wire) const;
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const std::vector<BelPin> &getWireBelPins(WireId wire) const;
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const std::vector<WireId> &getWires() const;
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// -------------------------------------------------
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PipId getPipByName(IdString name) const;
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void bindPip(PipId pip, NetInfo *net, PlaceStrength strength);
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void unbindPip(PipId pip);
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bool checkPipAvail(PipId pip) const;
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NetInfo *getBoundPipNet(PipId pip) const;
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WireId getConflictingPipWire(PipId pip) const;
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NetInfo *getConflictingPipNet(PipId pip) const;
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const std::vector<PipId> &getPips() const;
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Loc getPipLocation(PipId pip) const;
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IdString getPipName(PipId pip) const;
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IdString getPipType(PipId pip) const;
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std::vector<std::pair<IdString, std::string>> getPipAttrs(PipId pip) const;
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uint32_t getPipChecksum(PipId pip) const;
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WireId getPipSrcWire(PipId pip) const;
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WireId getPipDstWire(PipId pip) const;
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DelayInfo getPipDelay(PipId pip) const;
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const std::vector<BelPin> &getPipsDownhill(WireId wire) const;
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const std::vector<BelPin> &getPipsUphill(WireId wire) const;
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const std::vector<BelPin> &getWireAliases(WireId wire) const;
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BelId getPackagePinBel(const std::string &pin) const;
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std::string getBelPackagePin(BelId bel) const;
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// -------------------------------------------------
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GroupId getGroupByName(IdString name) const;
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IdString getGroupName(GroupId group) const;
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std::vector<GroupId> getGroups() const;
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std::vector<BelId> getGroupBels(GroupId group) const;
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std::vector<WireId> getGroupWires(GroupId group) const;
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std::vector<PipId> getGroupPips(GroupId group) const;
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std::vector<GroupId> getGroupGroups(GroupId group) const;
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// -------------------------------------------------
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delay_t estimateDelay(WireId src, WireId dst) const;
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delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const;
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delay_t getDelayEpsilon() const;
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delay_t getRipupDelayPenalty() const;
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float getDelayNS(delay_t v) const;
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DelayInfo getDelayFromNS(float ns) const;
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uint32_t getDelayChecksum(delay_t v) const;
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bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const;
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ArcBounds getRouteBoundingBox(WireId src, WireId dst) const;
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// -------------------------------------------------
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bool pack();
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bool place();
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bool route();
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// -------------------------------------------------
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std::vector<GraphicElement> getDecalGraphics(DecalId decal) const;
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DecalXY getBelDecal(BelId bel) const;
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DecalXY getWireDecal(WireId wire) const;
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DecalXY getPipDecal(PipId pip) const;
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DecalXY getGroupDecal(GroupId group) const;
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// -------------------------------------------------
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// Get the delay through a cell from one port to another, returning false
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// if no path exists. This only considers combinational delays, as required by the Arch API
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bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
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// getCellDelayInternal is similar to the above, but without false path checks and including clock to out delays
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// for internal arch use only
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bool getCellDelayInternal(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
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// Get the port class, also setting clockInfoCount to the number of TimingClockingInfos associated with a port
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TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const;
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// Get the TimingClockingInfo of a port
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TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const;
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// Return true if a port is a net
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bool isGlobalNet(const NetInfo *net) const;
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// -------------------------------------------------
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// Perform placement validity checks, returning false on failure (all
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// implemented in arch_place.cc)
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// Whether or not a given cell can be placed at a given Bel
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// This is not intended for Bel type checks, but finer-grained constraints
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// such as conflicting set/reset signals, etc
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bool isValidBelForCell(CellInfo *cell, BelId bel) const;
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// Return true whether all Bels at a given location are valid
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bool isBelLocationValid(BelId bel) const;
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// Helper function for above
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bool logicCellsCompatible(const CellInfo **it, const size_t size) const;
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// -------------------------------------------------
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// Assign architecure-specific arguments to nets and cells, which must be
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// called between packing or further
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// netlist modifications, and validity checks
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void assignArchInfo();
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void assignCellInfo(CellInfo *cell);
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// -------------------------------------------------
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BelPin getIOBSharingPLLPin(BelId pll, IdString pll_pin) const;
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int getDrivenGlobalNetwork(BelId bel) const;
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static const std::string defaultPlacer;
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static const std::vector<std::string> availablePlacers;
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static const std::string defaultRouter;
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static const std::vector<std::string> availableRouters;
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};
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NEXTPNR_NAMESPACE_END
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