In the Gowin chips, the tiles are connected to each other by a one-hop
wire, among others. There are 4 one-hop wires, of which 2 are shared
between north/south and east/west, have three names: e.g. SN10 and N110
and S110.
But only one of them, the first, occurs as a sink for PIP, that is, you
can not get a route that would pass through the S110 for example.
This commit corrects the names to SN?0 and EW?0 at the wire creation
stage to avoid dead wires.
In addition, the SN?0 and EW?0 are among the few sinks for global clock
wires and now there is the possibility of a more optimal clock routing.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
bd0af4052c