0afa0da19f
This lowers the CPU cost of using the flat wire map in router2, and should use less memory as well. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
10 lines
335 B
Plaintext
10 lines
335 B
Plaintext
[submodule "tests"]
|
|
path = tests
|
|
url = https://github.com/YosysHQ/nextpnr-tests
|
|
[submodule "fpga-interchange-schema"]
|
|
path = 3rdparty/fpga-interchange-schema
|
|
url = https://github.com/SymbiFlow/fpga-interchange-schema.git
|
|
[submodule "3rdparty/abseil-cpp"]
|
|
path = 3rdparty/abseil-cpp
|
|
url = https://github.com/abseil/abseil-cpp.git
|