487 lines
14 KiB
C++
487 lines
14 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <iostream>
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#include <math.h>
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#include "nextpnr.h"
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#include "embed.h"
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#include "placer1.h"
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#include "placer_heap.h"
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#include "router1.h"
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#include "router2.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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static std::tuple<int, int, std::string> split_identifier_name(const std::string &name)
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{
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size_t first_slash = name.find('/');
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NPNR_ASSERT(first_slash != std::string::npos);
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size_t second_slash = name.find('/', first_slash + 1);
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NPNR_ASSERT(second_slash != std::string::npos);
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return std::make_tuple(std::stoi(name.substr(1, first_slash)),
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std::stoi(name.substr(first_slash + 2, second_slash - first_slash)),
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name.substr(second_slash + 1));
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};
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// -----------------------------------------------------------------------
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void IdString::initialize_arch(const BaseCtx *ctx) {
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#define X(t) initialize_add(ctx, #t, ID_##t);
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#include "constids.inc"
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#undef X
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}
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// ---------------------------------------------------------------
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static const ChipInfoPOD *get_chip_info(ArchArgs::ArchArgsTypes chip)
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{
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std::string chipdb;
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if (chip == ArchArgs::LCMXO2_256HC) {
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chipdb = "machxo2/chipdb-256.bin";
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} else if (chip == ArchArgs::LCMXO2_640HC) {
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chipdb = "machxo2/chipdb-640.bin";
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} else if (chip == ArchArgs::LCMXO2_1200HC) {
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chipdb = "machxo2/chipdb-1200.bin";
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} else if (chip == ArchArgs::LCMXO2_2000HC) {
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chipdb = "machxo2/chipdb-2000.bin";
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} else if (chip == ArchArgs::LCMXO2_4000HC) {
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chipdb = "machxo2/chipdb-4000.bin";
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} else if (chip == ArchArgs::LCMXO2_7000HC) {
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chipdb = "machxo2/chipdb-7000.bin";
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} else {
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log_error("Unknown chip\n");
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}
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auto ptr = reinterpret_cast<const RelPtr<ChipInfoPOD> *>(get_chipdb(chipdb));
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if (ptr == nullptr)
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return nullptr;
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return ptr->get();
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}
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// ---------------------------------------------------------------
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Arch::Arch(ArchArgs args) : args(args)
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{
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chip_info = get_chip_info(args.type);
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if (chip_info == nullptr)
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log_error("Unsupported MachXO2 chip type.\n");
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if (chip_info->const_id_count != DB_CONST_ID_COUNT)
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log_error("Chip database 'bba' and nextpnr code are out of sync; please rebuild (or contact distribution "
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"maintainer)!\n");
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package_info = nullptr;
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for (int i = 0; i < chip_info->num_packages; i++) {
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if (args.package == chip_info->package_info[i].name.get()) {
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package_info = &(chip_info->package_info[i]);
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break;
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}
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}
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if (!package_info)
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log_error("Unsupported package '%s' for '%s'.\n", args.package.c_str(), getChipName().c_str());
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bel_to_cell.resize(chip_info->height * chip_info->width * max_loc_bels, nullptr);
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}
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bool Arch::isAvailable(ArchArgs::ArchArgsTypes chip) { return get_chip_info(chip) != nullptr; }
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std::string Arch::getChipName() const
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{
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if (args.type == ArchArgs::LCMXO2_256HC) {
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return "LCMXO2-256HC";
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} else if (args.type == ArchArgs::LCMXO2_640HC) {
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return "LCMXO2-640HC";
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} else if (args.type == ArchArgs::LCMXO2_1200HC) {
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return "LCMXO2-1200HC";
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} else if (args.type == ArchArgs::LCMXO2_2000HC) {
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return "LCMXO2-2000HC";
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} else if (args.type == ArchArgs::LCMXO2_4000HC) {
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return "LCMXO2-4000HC";
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} else if (args.type == ArchArgs::LCMXO2_7000HC) {
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return "LCMXO2-7000HC";
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} else {
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log_error("Unknown chip\n");
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}
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}
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IdString Arch::archArgsToId(ArchArgs args) const
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{
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if (args.type == ArchArgs::LCMXO2_256HC) {
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return id("lcmxo2_256hc");
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} else if (args.type == ArchArgs::LCMXO2_640HC) {
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return id("lcmxo2_640hc");
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} else if (args.type == ArchArgs::LCMXO2_1200HC) {
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return id("lcmxo2_1200hc");
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} else if (args.type == ArchArgs::LCMXO2_2000HC) {
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return id("lcmxo2_2000hc");
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} else if (args.type == ArchArgs::LCMXO2_4000HC) {
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return id("lcmxo2_4000hc");
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} else if (args.type == ArchArgs::LCMXO2_7000HC) {
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return id("lcmxo2_7000hc");
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}
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return IdString();
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}
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// ---------------------------------------------------------------
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BelId Arch::getBelByName(IdString name) const
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{
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BelId ret;
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auto it = bel_by_name.find(name);
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if (it != bel_by_name.end())
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return it->second;
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Location loc;
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std::string basename;
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std::tie(loc.x, loc.y, basename) = split_identifier_name(name.str(this));
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ret.location = loc;
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const TileTypePOD *tilei = tileInfo(ret);
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for (int i = 0; i < tilei->num_bels; i++) {
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if (std::strcmp(tilei->bel_data[i].name.get(), basename.c_str()) == 0) {
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ret.index = i;
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break;
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}
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}
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if (ret.index >= 0)
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bel_by_name[name] = ret;
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return ret;
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}
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BelId Arch::getBelByLocation(Loc loc) const
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{
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BelId ret;
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if(loc.x >= chip_info->width || loc.y >= chip_info->height)
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return BelId();
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ret.location.x = loc.x;
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ret.location.y = loc.y;
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const TileTypePOD *tilei = tileInfo(ret);
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for(int i = 0; i < tilei->num_bels; i++) {
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if(tilei->bel_data[i].z == loc.z)
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{
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ret.index = i;
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return ret;
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}
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}
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return BelId();
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}
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BelRange Arch::getBelsByTile(int x, int y) const
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{
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BelRange br;
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br.b.cursor_tile = y * chip_info->width + x;
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br.e.cursor_tile = y * chip_info->width + x;
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br.b.cursor_index = 0;
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br.e.cursor_index = chip_info->tiles[y * chip_info->width + x].num_bels - 1;
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br.b.chip = chip_info;
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br.e.chip = chip_info;
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if (br.e.cursor_index == -1)
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++br.e.cursor_index;
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else
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++br.e;
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return br;
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}
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bool Arch::getBelGlobalBuf(BelId bel) const { return false; }
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const std::map<IdString, std::string> &Arch::getBelAttrs(BelId bel) const { return attrs_dummy; }
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WireId Arch::getBelPinWire(BelId bel, IdString pin) const
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{
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return WireId();
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}
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PortType Arch::getBelPinType(BelId bel, IdString pin) const
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{
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NPNR_ASSERT(bel != BelId());
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int num_bel_wires = tileInfo(bel)->bel_data[bel.index].num_bel_wires;
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const BelWirePOD *bel_wires = &*tileInfo(bel)->bel_data[bel.index].bel_wires;
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for(int i = 0; i < num_bel_wires; i++)
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if(bel_wires[i].port == pin.index)
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return PortType(bel_wires[i].dir);
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return PORT_INOUT;
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}
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std::vector<IdString> Arch::getBelPins(BelId bel) const
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{
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std::vector<IdString> ret;
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NPNR_ASSERT(bel != BelId());
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int num_bel_wires = tileInfo(bel)->bel_data[bel.index].num_bel_wires;
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const BelWirePOD *bel_wires = &*tileInfo(bel)->bel_data[bel.index].bel_wires;
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for(int i = 0; i < num_bel_wires; i++) {
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IdString id(bel_wires[i].port);
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ret.push_back(id);
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}
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return ret;
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}
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// ---------------------------------------------------------------
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WireId Arch::getWireByName(IdString name) const
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{
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return WireId();
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}
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IdString Arch::getWireName(WireId wire) const { return IdString(); }
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IdString Arch::getWireType(WireId wire) const { return IdString(); }
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const std::map<IdString, std::string> &Arch::getWireAttrs(WireId wire) const { return attrs_dummy; }
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uint32_t Arch::getWireChecksum(WireId wire) const
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{
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// FIXME
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return 0;
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}
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void Arch::bindWire(WireId wire, NetInfo *net, PlaceStrength strength)
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{
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}
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void Arch::unbindWire(WireId wire)
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{
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}
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bool Arch::checkWireAvail(WireId wire) const { return false; }
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NetInfo *Arch::getBoundWireNet(WireId wire) const { return nullptr; }
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NetInfo *Arch::getConflictingWireNet(WireId wire) const { return nullptr; }
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const std::vector<BelPin> &Arch::getWireBelPins(WireId wire) const { return bel_pin_dummy; }
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const std::vector<WireId> &Arch::getWires() const { return wire_id_dummy; }
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// ---------------------------------------------------------------
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PipId Arch::getPipByName(IdString name) const
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{
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return PipId();
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}
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IdString Arch::getPipName(PipId pip) const { return IdString(); }
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IdString Arch::getPipType(PipId pip) const { return IdString(); }
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const std::map<IdString, std::string> &Arch::getPipAttrs(PipId pip) const { return attrs_dummy; }
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uint32_t Arch::getPipChecksum(PipId wire) const
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{
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// FIXME
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return 0;
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}
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void Arch::bindPip(PipId pip, NetInfo *net, PlaceStrength strength)
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{
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}
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void Arch::unbindPip(PipId pip)
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{
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}
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bool Arch::checkPipAvail(PipId pip) const { return false; }
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NetInfo *Arch::getBoundPipNet(PipId pip) const { return nullptr; }
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NetInfo *Arch::getConflictingPipNet(PipId pip) const { return nullptr; }
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WireId Arch::getConflictingPipWire(PipId pip) const { return WireId(); }
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const std::vector<PipId> &Arch::getPips() const { return pip_id_dummy; }
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Loc Arch::getPipLocation(PipId pip) const { return Loc(); }
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WireId Arch::getPipSrcWire(PipId pip) const { return WireId(); }
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WireId Arch::getPipDstWire(PipId pip) const { return WireId(); }
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DelayInfo Arch::getPipDelay(PipId pip) const { return DelayInfo(); }
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const std::vector<PipId> &Arch::getPipsDownhill(WireId wire) const { return pip_id_dummy; }
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const std::vector<PipId> &Arch::getPipsUphill(WireId wire) const { return pip_id_dummy; }
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const std::vector<PipId> &Arch::getWireAliases(WireId wire) const { return pip_id_dummy; }
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// ---------------------------------------------------------------
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GroupId Arch::getGroupByName(IdString name) const { return GroupId(); }
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IdString Arch::getGroupName(GroupId group) const { return IdString(); }
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std::vector<GroupId> Arch::getGroups() const
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{
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std::vector<GroupId> ret;
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return ret;
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}
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const std::vector<BelId> &Arch::getGroupBels(GroupId group) const { return bel_id_dummy; }
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const std::vector<WireId> &Arch::getGroupWires(GroupId group) const { return wire_id_dummy; }
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const std::vector<PipId> &Arch::getGroupPips(GroupId group) const { return pip_id_dummy; }
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const std::vector<GroupId> &Arch::getGroupGroups(GroupId group) const { return group_id_dummy; }
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// ---------------------------------------------------------------
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delay_t Arch::estimateDelay(WireId src, WireId dst) const
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{
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return 0;
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}
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delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
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{
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return 0;
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}
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bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const { return false; }
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ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
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{
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ArcBounds bb;
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return bb;
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}
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// ---------------------------------------------------------------
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bool Arch::place()
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{
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std::string placer = str_or_default(settings, id("placer"), defaultPlacer);
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if (placer == "sa") {
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bool retVal = placer1(getCtx(), Placer1Cfg(getCtx()));
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getCtx()->settings[getCtx()->id("place")] = 1;
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archInfoToAttributes();
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return retVal;
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} else {
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log_error("MachXO2 architecture does not support placer '%s'\n", placer.c_str());
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}
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}
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bool Arch::route()
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{
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std::string router = str_or_default(settings, id("router"), defaultRouter);
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bool result;
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if (router == "router1") {
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result = router1(getCtx(), Router1Cfg(getCtx()));
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} else if (router == "router2") {
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router2(getCtx(), Router2Cfg(getCtx()));
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result = true;
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} else {
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log_error("MachXO2 architecture does not support router '%s'\n", router.c_str());
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}
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getCtx()->settings[getCtx()->id("route")] = 1;
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archInfoToAttributes();
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return result;
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}
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// ---------------------------------------------------------------
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const std::vector<GraphicElement> &Arch::getDecalGraphics(DecalId decal) const
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{
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return graphic_element_dummy;
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}
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DecalXY Arch::getBelDecal(BelId bel) const { return DecalXY(); }
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DecalXY Arch::getWireDecal(WireId wire) const { return DecalXY(); }
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DecalXY Arch::getPipDecal(PipId pip) const { return DecalXY(); }
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DecalXY Arch::getGroupDecal(GroupId group) const { return DecalXY(); }
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// ---------------------------------------------------------------
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bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
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{
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return false;
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}
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// Get the port class, also setting clockPort if applicable
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TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const
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{
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return TMG_IGNORE;
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}
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TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port, int index) const
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{
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return TimingClockingInfo();
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}
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bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
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{
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// FIXME: Unlike ECP5, SLICEs in a given tile do not share a clock, so
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// any SLICE Cell is valid for any BEL, even if some cells are already
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// bound to BELs in the tile. However, this may need to be filled in once
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// more than one LUT4 and DFF type is supported.
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return true;
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}
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bool Arch::isBelLocationValid(BelId bel) const
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{
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// FIXME: Same deal as isValidBelForCell.
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return true;
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}
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#ifdef WITH_HEAP
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const std::string Arch::defaultPlacer = "heap";
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#else
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const std::string Arch::defaultPlacer = "sa";
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#endif
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const std::vector<std::string> Arch::availablePlacers = {"sa",
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#ifdef WITH_HEAP
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"heap"
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#endif
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};
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const std::string Arch::defaultRouter = "router1";
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const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
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void Arch::assignArchInfo()
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{
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}
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bool Arch::cellsCompatible(const CellInfo **cells, int count) const
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{
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return false;
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}
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NEXTPNR_NAMESPACE_END
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