This chip is used in the Tangnano9k board.
* all parameters of the rPLL primitive are supported;
* all PLL outputs are treated as clock sources and optimized routing
is applied to them;
* primitive rPLL on different chips has a completely different
structure: for example in GW1N-1 it takes two cells, and in GW1NR-9C
as many as four, despite this unification was carried out and
different chips are processed by the same functions, but this led to
the fact that you can not use the PLL chip GW1N-1 with the old
apicula bases - will issue a warning and refuse to encode primitive.
In other cases compatibility is supported.
* Cosmetic change: the usage report shows the rPLL names without any
service bels.
* I use ctx->idf() on occasion, it's not a total redesign.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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