26 lines
653 B
VHDL
26 lines
653 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity testbench is
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end entity;
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architecture rtl of testbench is
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signal clk : STD_LOGIC;
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signal led : STD_LOGIC_VECTOR(3 downto 0);
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begin
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process begin
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clk <= '0';
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wait for 4 ns;
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clk <= '1';
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wait for 4 ns;
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end process;
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uut: entity work.name port map(clki_PAD_PAD => clk, led_0_OUTBUF_OUT => led(0), led_1_OUTBUF_OUT => led(1), led_2_OUTBUF_OUT => led(2), led_3_OUTBUF_OUT => led(3));
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process
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begin
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report "led = " & std_logic'image(led(3)) & std_logic'image(led(2)) & std_logic'image(led(1)) & std_logic'image(led(0));
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wait on led;
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end process;
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end rtl;
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