25 lines
355 B
Verilog
25 lines
355 B
Verilog
module top (
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input clki,
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output [3:0] led
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);
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(* keep *)
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wire led_unused;
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wire clk;
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BUFGCTRL clk_gb (
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.I0(clki),
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.CE0(1'b1),
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.CE1(1'b0),
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.S0(1'b1),
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.S1(1'b0),
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.IGNORE0(1'b0),
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.IGNORE1(1'b0),
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.O(clk)
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);
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attosoc soc(.clk(clk), .led({led_unused, led}));
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endmodule
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