55 lines
1.0 KiB
Plaintext
55 lines
1.0 KiB
Plaintext
read_verilog blinky.v
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chparam -set LOG2DELAY 0
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#synth_xilinx -top blinky
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#begin:
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read_verilog -lib +/xilinx/cells_sim.v
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read_verilog -lib +/xilinx/cells_xtra.v
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# read_verilog -lib +/xilinx/brams_bb.v
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# read_verilog -lib +/xilinx/drams_bb.v
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hierarchy -check -top blinky
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#flatten: (only if -flatten)
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proc
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flatten
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#coarse:
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synth -run coarse
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#bram:
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# memory_bram -rules +/xilinx/brams.txt
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# techmap -map +/xilinx/brams_map.v
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#
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#dram:
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# memory_bram -rules +/xilinx/drams.txt
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# techmap -map +/xilinx/drams_map.v
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fine:
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opt -fast -full
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memory_map
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dffsr2dff
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# dff2dffe
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opt -full
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techmap -map +/techmap.v #-map +/xilinx/arith_map.v
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opt -fast
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map_luts:
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abc -luts 2:2,3,6:5 #,10,20 [-dff]
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clean
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map_cells:
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techmap -map +/xilinx/cells_map.v
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dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT
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clean
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check:
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hierarchy -check
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stat
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check -noinit
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#edif: (only if -edif)
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# write_edif <file-name>
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write_json blinky.json
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