41 lines
818 B
Verilog
41 lines
818 B
Verilog
module top (
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input clk, resetn,
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output trap,
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output mem_valid,
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output mem_instr,
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input mem_ready,
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output [31:0] mem_addr,
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output [31:0] mem_wdata,
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output [ 3:0] mem_wstrb,
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input [31:0] mem_rdata
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);
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wire gclk;
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BUFGCTRL clk_gb (
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.I0(clk),
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.CE0(1'b1),
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.S0(1'b1),
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.O(gclk)
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);
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picorv32 #(
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.ENABLE_COUNTERS(0),
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.TWO_STAGE_SHIFT(0),
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.CATCH_MISALIGN(0),
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.CATCH_ILLINSN(0)
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) cpu (
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.clk (gclk ),
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.resetn (resetn ),
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.trap (trap ),
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.mem_valid(mem_valid),
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.mem_instr(mem_instr),
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.mem_ready(mem_ready),
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.mem_addr (mem_addr ),
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.mem_wdata(mem_wdata),
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.mem_wstrb(mem_wstrb),
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.mem_rdata(mem_rdata)
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);
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endmodule
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