263 lines
11 KiB
C++
263 lines
11 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
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* Copyright (C) 2018 David Shah <david@symbioticeda.com>
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* Copyright (C) 2018 Serge Bazanski <q3k@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "xdl.h"
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#include <cctype>
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#include <vector>
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#include "cells.h"
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#include "log.h"
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#include "nextpnr.h"
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#include "util.h"
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#include "torc/Physical.hpp"
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using namespace torc::architecture::xilinx;
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using namespace torc::physical;
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NEXTPNR_NAMESPACE_BEGIN
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void write_xdl(const Context *ctx, std::ostream &out)
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{
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XdlExporter exporter(out);
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auto designPtr = Factory::newDesignPtr("name", torc_info->ddb->getDeviceName(), ctx->args.package, "-1", "");
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std::unordered_map<int32_t, InstanceSharedPtr> site_to_instance;
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std::vector<std::pair<std::string, std::string>> lut_inputs;
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lut_inputs.reserve(6);
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auto bel_to_lut = [](const BelId bel) {
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switch (torc_info->bel_to_loc[bel.index].z) {
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case 0:
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case 4:
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return "A";
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break;
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case 1:
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case 5:
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return "B";
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break;
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case 2:
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case 6:
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return "C";
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break;
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case 3:
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case 7:
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return "D";
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break;
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default:
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throw;
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}
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};
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for (const auto &cell : ctx->cells) {
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const char *type;
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if (cell.second->type == id_SLICE_LUT6)
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type = "SLICEL";
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else if (cell.second->type == id_IOB33 || cell.second->type == id_BUFGCTRL || cell.second->type == id_PS7)
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type = cell.second->type.c_str(ctx);
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else
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log_error("Unsupported cell type '%s'.\n", cell.second->type.c_str(ctx));
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auto site_index = torc_info->bel_to_site_index[cell.second->bel.index];
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auto ret = site_to_instance.emplace(site_index, nullptr);
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InstanceSharedPtr instPtr;
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if (ret.second) {
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instPtr = Factory::newInstancePtr(cell.second->name.str(ctx), type, "", "");
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auto b = designPtr->addInstance(instPtr);
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assert(b);
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ret.first->second = instPtr;
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const auto &tile_info = torc_info->bel_to_tile_info(cell.second->bel.index);
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instPtr->setTile(tile_info.getName());
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instPtr->setSite(torc_info->bel_to_name(cell.second->bel.index));
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} else
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instPtr = ret.first->second;
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if (cell.second->type == id_SLICE_LUT6) {
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std::string setting, name, value;
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const std::string lut = bel_to_lut(cell.second->bel);
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setting = lut + "6LUT";
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value = "#LUT:O6=";
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lut_inputs.clear();
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if (get_net_or_empty(cell.second.get(), id_I1))
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lut_inputs.emplace_back("A1", "~A1");
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if (get_net_or_empty(cell.second.get(), id_I2))
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lut_inputs.emplace_back("A2", "~A2");
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if (get_net_or_empty(cell.second.get(), id_I3))
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lut_inputs.emplace_back("A3", "~A3");
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if (get_net_or_empty(cell.second.get(), id_I4))
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lut_inputs.emplace_back("A4", "~A4");
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if (get_net_or_empty(cell.second.get(), id_I5))
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lut_inputs.emplace_back("A5", "~A5");
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if (get_net_or_empty(cell.second.get(), id_I6))
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lut_inputs.emplace_back("A6", "~A6");
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const auto &init = cell.second->params[ctx->id("INIT")];
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// Assume from Yosys that INIT masks of less than 32 bits are output as uint32_t
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if (lut_inputs.size() < 6) {
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auto init_as_uint = boost::lexical_cast<uint32_t>(init);
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NPNR_ASSERT(init_as_uint < (1ull << (1u << lut_inputs.size())));
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if (lut_inputs.empty())
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value += init;
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else {
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unsigned n = 0;
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for (unsigned o = 0; o < (1u << lut_inputs.size()); ++o) {
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if (!((init_as_uint >> o) & 1))
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continue;
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if (n++ > 0)
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value += "+";
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value += "(";
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value += (o & 1) ? lut_inputs[0].first : lut_inputs[0].second;
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for (unsigned i = 1; i < lut_inputs.size(); ++i) {
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value += "*";
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value += o & (1 << i) ? lut_inputs[i].first : lut_inputs[i].second;
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}
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value += ")";
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}
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}
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}
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// Otherwise as a bit string
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else {
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NPNR_ASSERT(init.size() == (1u << lut_inputs.size()));
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unsigned n = 0;
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for (unsigned i = 0; i < init.size(); ++i) {
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if (init[init.size()-1-i] == '0')
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continue;
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if (n++ > 0)
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value += "+";
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value += "(";
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value += (i & 1) ? lut_inputs[0].first : lut_inputs[0].second;
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for (unsigned j = 1; j < lut_inputs.size(); ++j) {
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value += "*";
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value += i & (1 << j) ? lut_inputs[j].first : lut_inputs[j].second;
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}
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value += ")";
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}
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}
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auto it = cell.second->params.find(ctx->id("LUT_NAME"));
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if (it != cell.second->params.end())
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name = it->second;
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else
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name = cell.second->name.str(ctx);
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boost::replace_all(name, ":", "\\:");
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instPtr->setConfig(setting, name, value);
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auto O = get_net_or_empty(cell.second.get(), id_O);
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if (O) {
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setting = lut;
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setting += "USED";
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instPtr->setConfig(setting, "", "0");
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}
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auto OQ = get_net_or_empty(cell.second.get(), id_OQ);
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if (OQ) {
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setting = lut;
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setting += "FF";
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name = OQ->name.str(ctx);
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boost::replace_all(name, ":", "\\:");
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instPtr->setConfig(setting, name, "#FF");
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instPtr->setConfig(setting + "MUX", "", "O6");
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instPtr->setConfig(setting + "INIT", "", "INIT" + cell.second->params.at(ctx->id("DFF_INIT")));
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assert(cell.second->params.at(ctx->id("SET_NORESET")) == "0"); // TODO
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instPtr->setConfig(setting + "SR", "", "SRLOW");
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NPNR_ASSERT(!cell.second->lcInfo.negClk); // TODO
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instPtr->setConfig("CLKINV", "", "CLK");
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instPtr->setConfig("SRUSEDMUX", "", "IN");
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instPtr->setConfig("CEUSEDMUX", "", "IN");
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instPtr->setConfig("SYNC_ATTR", "", "ASYNC");
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}
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} else if (cell.second->type == id_IOB33) {
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if (get_net_or_empty(cell.second.get(), id_I)) {
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instPtr->setConfig("IUSED", "", "0");
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instPtr->setConfig("IBUF_LOW_PWR", "", "TRUE");
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instPtr->setConfig("ISTANDARD", "", "LVCMOS33");
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} else {
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instPtr->setConfig("OUSED", "", "0");
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instPtr->setConfig("OSTANDARD", "", "LVCMOS33");
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instPtr->setConfig("DRIVE", "", "12");
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instPtr->setConfig("SLEW", "", "SLOW");
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}
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} else if (cell.second->type == id_BUFGCTRL) {
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auto it = cell.second->params.find(ctx->id("PRESELECT_I0"));
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instPtr->setConfig("PRESELECT_I0", "", it != cell.second->params.end() ? it->second : "FALSE");
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instPtr->setConfig("CE0INV", "", "CE0");
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instPtr->setConfig("S0INV", "", "S0");
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instPtr->setConfig("IGNORE0INV", "", "IGNORE0");
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instPtr->setConfig("CE1INV", "", "CE1");
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instPtr->setConfig("S1INV", "", "S1");
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instPtr->setConfig("IGNORE1INV", "", "IGNORE1");
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} else if (cell.second->type == id_PS7) {
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} else
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log_error("Unsupported cell type '%s'.\n", cell.second->type.c_str(ctx));
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}
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for (const auto &net : ctx->nets) {
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const auto &driver = net.second->driver;
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auto site_index = torc_info->bel_to_site_index[driver.cell->bel.index];
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auto instPtr = site_to_instance.at(site_index);
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auto netPtr = Factory::newNetPtr(net.second->name.str(ctx));
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auto pin_name = driver.port.str(ctx);
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// For all LUT based inputs and outputs (I1-I6,O,OQ,OMUX) then change the I/O into the LUT
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if (driver.cell->type == id_SLICE_LUT6 && (pin_name[0] == 'I' || pin_name[0] == 'O')) {
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const auto lut = bel_to_lut(driver.cell->bel);
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pin_name[0] = lut[0];
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}
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auto pinPtr = Factory::newInstancePinPtr(instPtr, pin_name);
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netPtr->addSource(pinPtr);
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for (const auto &user : net.second->users) {
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site_index = torc_info->bel_to_site_index[user.cell->bel.index];
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instPtr = site_to_instance.at(site_index);
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pin_name = user.port.str(ctx);
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// For all LUT based inputs and outputs (I1-I6,O,OQ,OMUX) then change the I/O into the LUT
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if (user.cell->type == id_SLICE_LUT6 && (pin_name[0] == 'I' || pin_name[0] == 'O')) {
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const auto lut = bel_to_lut(user.cell->bel);
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pin_name[0] = lut[0];
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}
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pinPtr = Factory::newInstancePinPtr(instPtr, pin_name);
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netPtr->addSink(pinPtr);
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}
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auto b = designPtr->addNet(netPtr);
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assert(b);
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for (const auto &i : net.second->wires) {
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const auto &pip_map = i.second;
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if (pip_map.pip == PipId())
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continue;
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ExtendedWireInfo ewi_src(*torc_info->ddb, torc_info->pip_to_arc[pip_map.pip.index].getSourceTilewire());
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ExtendedWireInfo ewi_dst(*torc_info->ddb, torc_info->pip_to_arc[pip_map.pip.index].getSinkTilewire());
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auto p = Factory::newPip(ewi_src.mTileName, ewi_src.mWireName, ewi_dst.mWireName,
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ePipUnidirectionalBuffered);
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netPtr->addPip(p);
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}
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}
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exporter(designPtr);
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}
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NEXTPNR_NAMESPACE_END
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