34 lines
620 B
Verilog
34 lines
620 B
Verilog
// Modified from:
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// https://github.com/tinyfpga/TinyFPGA-A-Series/tree/master/template_a2
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// https://tinyfpga.com/a-series-guide.html used as a basis.
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module top (
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(* LOC="21" *)
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inout pin6,
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(* LOC="26" *)
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inout pin9_jtgnb,
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(* LOC="27" *)
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inout pin10_sda,
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);
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wire clk;
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OSCH #(
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.NOM_FREQ("2.08")
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) internal_oscillator_inst (
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.STDBY(1'b0),
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.OSC(clk)
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);
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reg [23:0] led_timer;
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always @(posedge clk) begin
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led_timer <= led_timer + 1;
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end
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// left side of board
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assign pin9_jtgnb = led_timer[23];
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assign pin10_sda = led_timer[22];
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assign pin6 = led_timer[21];
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endmodule
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