26 lines
618 B
Verilog
26 lines
618 B
Verilog
module blinky_tb;
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reg clk;
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always #5 clk = (clk === 1'b0);
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wire led0, led1, led2, led3;
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chip uut (
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.\clki$iob.PAD.PAD (clk),
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.\led0$iob.OUTBUF.OUT (led0),
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.\led1$iob.OUTBUF.OUT (led1),
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.\led2$iob.OUTBUF.OUT (led2),
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.\led3$iob.OUTBUF.OUT (led3)
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);
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initial begin
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// $dumpfile("blinky_tb.vcd");
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// $dumpvars(0, blinky_tb);
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$monitor(led0, led1, led2, led3);
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//repeat (10) begin
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// repeat (900000) @(posedge clk);
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// $display(led0, led1, led2, led3);
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//end
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//$finish;
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end
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endmodule
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