c82654d003
- MUX2_LUT5, MUX2_LUT6, MUX2_LUT7 and MUX2_LUT8 support; - storing a common class of files in extra_data; - misc fixes. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
304 lines
12 KiB
Python
304 lines
12 KiB
Python
from os import path
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import sys
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import importlib.resources
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import pickle
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import gzip
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import re
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import argparse
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sys.path.append(path.join(path.dirname(__file__), "../.."))
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from himbaechel_dbgen.chip import *
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from apycula import chipdb
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# Z of the bels
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# sync with C++ part!
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LUT0_Z = 0 # z(DFFx) = z(LUTx) + 1
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LUT7_Z = 14
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MUX20_Z = 16
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MUX21_Z = 18
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MUX23_Z = 22
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MUX27_Z = 29
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VCC_Z = 277
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GND_Z = 278
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@dataclass
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class TileExtraData(BBAStruct):
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tile_class: IdString # The general functionality of the slightly different tiles,
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# let's say the behavior of LUT+DFF in the tiles are completely identical,
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# but one of them also contains clock-wire switches,
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# then we assign them to the same LOGIC class.
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def serialise_lists(self, context: str, bba: BBAWriter):
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pass
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def serialise(self, context: str, bba: BBAWriter):
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bba.u32(self.tile_class.index)
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created_tiletypes = set()
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# u-turn at the rim
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uturnlut = {'N': 'S', 'S': 'N', 'E': 'W', 'W': 'E'}
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def uturn(db: chipdb, x: int, y: int, wire: str):
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m = re.match(r"([NESW])([128]\d)(\d)", wire)
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if m:
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direction, num, segment = m.groups()
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# wires wrap around the edges
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# assumes 0-based indexes
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if y < 0:
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y = -1 - y
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direction = uturnlut[direction]
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if x < 0:
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x = -1 - x
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direction = uturnlut[direction]
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if y > db.rows - 1:
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y = 2 * db.rows - 1 - y
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direction = uturnlut[direction]
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if x > db.cols - 1:
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x = 2 * db.cols - 1 - x
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direction = uturnlut[direction]
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wire = f'{direction}{num}{segment}'
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return (x, y, wire)
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def create_nodes(chip: Chip, db: chipdb):
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# : (x, y)
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dirs = { 'N': (0, -1), 'S': (0, 1), 'W': (-1, 0), 'E': (1, 0) }
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X = db.cols
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Y = db.rows
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global_nodes = {}
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for y in range(Y):
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for x in range(X):
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nodes = []
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# SN and EW
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for i in [1, 2]:
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nodes.append([NodeWire(x, y, f'SN{i}0'),
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NodeWire(*uturn(db, x, y - 1, f'N1{i}1')),
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NodeWire(*uturn(db, x, y + 1, f'S1{i}1'))])
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nodes.append([NodeWire(x, y, f'EW{i}0'),
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NodeWire(*uturn(db, x - 1, y, f'W1{i}1')),
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NodeWire(*uturn(db, x + 1, y, f'E1{i}1'))])
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for d, offs in dirs.items():
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# 1-hop
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for i in [0, 3]:
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nodes.append([NodeWire(x, y, f'{d}1{i}0'),
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NodeWire(*uturn(db, x + offs[0], y + offs[1], f'{d}1{i}1'))])
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# 2-hop
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for i in range(8):
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nodes.append([NodeWire(x, y, f'{d}2{i}0'),
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NodeWire(*uturn(db, x + offs[0], y + offs[1], f'{d}2{i}1')),
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NodeWire(*uturn(db, x + offs[0] * 2, y + offs[1] * 2, f'{d}2{i}2'))])
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# 4-hop
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for i in range(4):
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nodes.append([NodeWire(x, y, f'{d}8{i}0'),
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NodeWire(*uturn(db, x + offs[0] * 4, y + offs[1] * 4, f'{d}8{i}4')),
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NodeWire(*uturn(db, x + offs[0] * 8, y + offs[1] * 8, f'{d}8{i}8'))])
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# I0 for MUX2_LUT8
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if x < X - 1 and chip.tile_type_at(x, y).extra_data.tile_class == chip.strs.id('LOGIC') and chip.tile_type_at(x, y).extra_data.tile_class == chip.strs.id('LOGIC'):
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nodes.append([NodeWire(x, y, 'OF30'),
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NodeWire(x + 1, y, 'OF3')])
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for node in nodes:
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chip.add_node(node)
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# VCC and VSS sources in the all tiles
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global_nodes.setdefault('GND', []).append(NodeWire(x, y, 'VSS'))
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global_nodes.setdefault('VCC', []).append(NodeWire(x, y, 'VCC'))
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for node in global_nodes.values():
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chip.add_node(node)
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# About X and Y as parameters - in some cases, the type of manufacturer's tile
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# is not different, but some wires are not physically present, that is, routing
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# depends on the location of otherwise identical tiles. There are many options
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# for taking this into account, but for now we make a distinction here, by
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# coordinates.
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def create_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
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pips = db.grid[y][x].pips
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for dst, srcs in pips.items():
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if not tt.has_wire(dst):
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tt.create_wire(dst)
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for src in srcs.keys():
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if not tt.has_wire(src):
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tt.create_wire(src)
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tt.create_pip(src, dst)
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def create_null_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
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if ttyp in created_tiletypes:
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return ttyp
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typename = "NULL"
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tt = chip.create_tile_type(f"{typename}_{ttyp}")
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tt.extra_data = TileExtraData(chip.strs.id(typename))
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create_switch_matrix(tt, db, x, y)
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return ttyp
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# responsible nodes, there will be IO banks, configuration, etc.
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def create_corner_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
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if ttyp in created_tiletypes:
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return ttyp
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typename = "CORNER"
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tt = chip.create_tile_type(f"{typename}_{ttyp}")
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tt.extra_data = TileExtraData(chip.strs.id(typename))
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if x == 0 and y == 0:
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# GND is the logic low level generator
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tt.create_wire('VSS', 'GND')
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gnd = tt.create_bel('GND', 'GND', z = GND_Z)
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tt.add_bel_pin(gnd, "G", "VSS", PinType.OUTPUT)
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# VCC is the logic high level generator
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tt.create_wire('VCC', 'VCC')
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gnd = tt.create_bel('VCC', 'VCC', z = VCC_Z)
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tt.add_bel_pin(gnd, "V", "VCC", PinType.OUTPUT)
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create_switch_matrix(tt, db, x, y)
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return ttyp
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# simple IO - only A and B
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def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
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if ttyp in created_tiletypes:
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return ttyp
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typename = "IO"
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tt = chip.create_tile_type(f"{typename}_{ttyp}")
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tt.extra_data = TileExtraData(chip.strs.id(typename))
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for i in range(2):
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name = ['IOBA', 'IOBB'][i]
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# wires
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portmap = db.grid[y][x].bels[name].portmap
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tt.create_wire(portmap['I'], "IO_I")
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tt.create_wire(portmap['O'], "IO_I")
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# bels
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io = tt.create_bel(name, "IOB", z = i)
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tt.add_bel_pin(io, "I", portmap['I'], PinType.INPUT)
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tt.add_bel_pin(io, "O", portmap['O'], PinType.OUTPUT)
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create_switch_matrix(tt, db, x, y)
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return ttyp
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# XXX lut+dff only for now
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def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
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lut_inputs = ['A', 'B', 'C', 'D']
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if ttyp in created_tiletypes:
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return ttyp
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typename = "LOGIC"
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tt = chip.create_tile_type(f"{typename}_{ttyp}")
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tt.extra_data = TileExtraData(chip.strs.id(typename))
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# setup wires
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for i in range(8):
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for inp_name in lut_inputs:
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tt.create_wire(f"{inp_name}{i}", "LUT_INPUT")
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tt.create_wire(f"F{i}", "LUT_OUT")
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# experimental. the wire is false - it is assumed that DFF is always
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# connected to the LUT's output F{i}, but we can place primitives
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# arbitrarily and create a pass-through LUT afterwards.
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# just out of curiosity
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tt.create_wire(f"XD{i}", "FF_INPUT")
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tt.create_wire(f"Q{i}", "FF_OUT")
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for j in range(3):
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tt.create_wire(f"CLK{j}", "TILE_CLK")
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tt.create_wire(f"LSR{j}", "TILE_LSR")
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tt.create_wire(f"CE{j}", "TILE_CE")
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for j in range(8):
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tt.create_wire(f"OF{j}", "MUX_OUT")
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tt.create_wire(f"SEL{j}", "MUX_SEL")
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tt.create_wire("OF30", "MUX_OUT")
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# create logic cells
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for i in range(8):
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# LUT
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lut = tt.create_bel(f"LUT{i}", "LUT4", z = (i * 2 + 0))
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for j, inp_name in enumerate(lut_inputs):
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tt.add_bel_pin(lut, f"I{j}", f"{inp_name}{i}", PinType.INPUT)
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tt.add_bel_pin(lut, "F", f"F{i}", PinType.OUTPUT)
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if i < 6:
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# FF data can come from LUT output, but we pretend that we can use
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# any LUT input
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tt.create_pip(f"F{i}", f"XD{i}")
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for inp_name in lut_inputs:
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tt.create_pip(f"{inp_name}{i}", f"XD{i}")
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# FF
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ff = tt.create_bel(f"DFF{i}", "DFF", z =(i * 2 + 1))
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tt.add_bel_pin(ff, "D", f"XD{i}", PinType.INPUT)
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tt.add_bel_pin(ff, "CLK", f"CLK{i // 2}", PinType.INPUT)
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tt.add_bel_pin(ff, "Q", f"Q{i}", PinType.OUTPUT)
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tt.add_bel_pin(ff, "SET", f"LSR{i // 2}", PinType.INPUT)
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tt.add_bel_pin(ff, "RESET", f"LSR{i // 2}", PinType.INPUT)
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tt.add_bel_pin(ff, "PRESET", f"LSR{i // 2}", PinType.INPUT)
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tt.add_bel_pin(ff, "CLEAR", f"LSR{i // 2}", PinType.INPUT)
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tt.add_bel_pin(ff, "CE", f"CE{i // 2}", PinType.INPUT)
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# wide luts
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for i in range(4):
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ff = tt.create_bel(f"MUX{i * 2}", "MUX2_LUT5", z = MUX20_Z + i * 4)
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tt.add_bel_pin(ff, "I0", f"F{i * 2}", PinType.INPUT)
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tt.add_bel_pin(ff, "I1", f"F{i * 2 + 1}", PinType.INPUT)
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tt.add_bel_pin(ff, "O", f"OF{i * 2}", PinType.OUTPUT)
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tt.add_bel_pin(ff, "S0", f"SEL{i * 2}", PinType.INPUT)
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for i in range(2):
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ff = tt.create_bel(f"MUX{i * 4 + 1}", "MUX2_LUT6", z = MUX21_Z + i * 8)
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tt.add_bel_pin(ff, "I0", f"OF{i * 4 + 2}", PinType.INPUT)
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tt.add_bel_pin(ff, "I1", f"OF{i * 4}", PinType.INPUT)
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tt.add_bel_pin(ff, "O", f"OF{i * 4 + 1}", PinType.OUTPUT)
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tt.add_bel_pin(ff, "S0", f"SEL{i * 4 + 1}", PinType.INPUT)
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ff = tt.create_bel(f"MUX3", "MUX2_LUT7", z = MUX23_Z)
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tt.add_bel_pin(ff, "I0", f"OF5", PinType.INPUT)
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tt.add_bel_pin(ff, "I1", f"OF1", PinType.INPUT)
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tt.add_bel_pin(ff, "O", f"OF3", PinType.OUTPUT)
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tt.add_bel_pin(ff, "S0", f"SEL3", PinType.INPUT)
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ff = tt.create_bel(f"MUX7", "MUX2_LUT8", z = MUX27_Z)
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tt.add_bel_pin(ff, "I0", f"OF30", PinType.INPUT)
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tt.add_bel_pin(ff, "I1", f"OF3", PinType.INPUT)
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tt.add_bel_pin(ff, "O", f"OF7", PinType.OUTPUT)
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tt.add_bel_pin(ff, "S0", f"SEL7", PinType.INPUT)
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create_switch_matrix(tt, db, x, y)
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return ttyp
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def main():
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parser = argparse.ArgumentParser(description='Make Gowin BBA')
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parser.add_argument('-d', '--device', required=True)
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parser.add_argument('-o', '--output', default="out.bba")
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args = parser.parse_args()
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device = args.device
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with gzip.open(importlib.resources.files("apycula").joinpath(f"{device}.pickle"), 'rb') as f:
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db = pickle.load(f)
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X = db.cols;
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Y = db.rows;
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ch = Chip("gowin", device, X, Y)
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# Init constant ids
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ch.strs.read_constids(path.join(path.dirname(__file__), "constids.inc"))
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# The manufacturer distinguishes by externally identical tiles, so keep
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# these differences (in case it turns out later that there is a slightly
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# different routing or something like that).
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logic_tiletypes = {12, 13, 14, 15, 16, 17}
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io_tiletypes = {53, 55, 58, 59, 64, 65}
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# Setup tile grid
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for x in range(X):
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for y in range(Y):
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ttyp = db.grid[y][x].ttyp
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if (x == 0 or x == X - 1) and (y == 0 or y == Y - 1):
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assert ttyp not in created_tiletypes, "Duplication of corner types"
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ttyp = create_corner_tiletype(ch, db, x, y, ttyp)
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created_tiletypes.add(ttyp)
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ch.set_tile_type(x, y, f"CORNER_{ttyp}")
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continue
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if ttyp in logic_tiletypes:
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ttyp = create_logic_tiletype(ch, db, x, y, ttyp)
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created_tiletypes.add(ttyp)
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ch.set_tile_type(x, y, f"LOGIC_{ttyp}")
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elif ttyp in io_tiletypes:
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ttyp = create_io_tiletype(ch, db, x, y, ttyp)
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created_tiletypes.add(ttyp)
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ch.set_tile_type(x, y, f"IO_{ttyp}")
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else:
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ttyp = create_null_tiletype(ch, db, x, y, ttyp)
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created_tiletypes.add(ttyp)
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ch.set_tile_type(x, y, f"NULL_{ttyp}")
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# Create nodes between tiles
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create_nodes(ch, db)
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ch.write_bba(args.output)
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if __name__ == '__main__':
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main()
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