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cc273c1257
nextpnr/himbaechel/uarch/gowin
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YRabbit cc273c1257 gowin: Himbaechel. Handle SDP OCE 
Semi-dual port BSRAM (in Gowin terminology) has the same feature as
Single Port - the CE and OCE signals must be synchronized.

Such a sin has not yet been noticed for Dual Port.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2024-02-09 08:04:08 +01:00
..
CMakeLists.txt gowin: Himbaechel. Add GW1NZ-1 BSRAM. 2023-11-26 13:08:09 +01:00
constids.inc gowin: Himbaechel. Deal with SP BSRAM ports. 2024-01-23 14:00:29 +01:00
cst.cc gowin: Himbaechel. Extend clock router 2023-09-08 09:15:35 +02:00
cst.h gowin: Himbaechel. Add constraint file processing. 2023-08-31 08:28:09 +02:00
globals.cc gowin: Himbaechel. Edit message text. 2024-02-09 08:03:56 +01:00
globals.h gowin: Himbaechel. Add a clock router. 2023-08-31 08:28:09 +02:00
gowin_arch_gen.py gowin: Himbaechel. Add BSRAM for all chips. 2023-11-26 13:08:09 +01:00
gowin_utils.cc gowin: Himbaechel. Add BSRAM for all chips. 2023-11-26 13:08:09 +01:00
gowin_utils.h gowin: Himbaechel. Deal with SP BSRAM ports. 2024-01-23 14:00:29 +01:00
gowin.cc gowin: Himbaechel. Deal with SP BSRAM ports. 2024-01-23 14:00:29 +01:00
gowin.h gowin: Himbaechel. Add BSRAM for all chips. 2023-11-26 13:08:09 +01:00
pack.cc gowin: Himbaechel. Handle SDP OCE 2024-02-09 08:04:08 +01:00
pack.h gowin: Himbaechel. Add ALU. 2023-08-31 08:28:09 +02:00