104 lines
3.4 KiB
C++
104 lines
3.4 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2021-22 gatecat <gatecat@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef FAB_CFG_H
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#define FAB_CFG_H
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#include "fab_defs.h"
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#include "hashlib.h"
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#include "idstring.h"
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#include "nextpnr_assertions.h"
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#include "nextpnr_namespaces.h"
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#include <string>
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#include <vector>
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NEXTPNR_NAMESPACE_BEGIN
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/*
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This set of structures is designed to enumerate the different configurable options for a fabulous architecture,
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affecting the packer etc...
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*/
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struct ControlSetConfig
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{
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/*
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CLB signal routing masks for fast validity checking
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for each unique CLK/CE/SR input to a CLB, add an entry to this vector, and set the bits to 1 for each ff that
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signal can drive for a CLB with 8 FFs and 2 clocks split at halfway, the first entry would be 0x0F and the second
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0xF0
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*/
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std::vector<route_mask_t> routing; // default 1 shared between all
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bool have_signal = true;
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int can_mask = -1;
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bool can_invert = false;
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};
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struct LogicConfig
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{
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// ** Core CLB config
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unsigned lc_per_clb = 8; // number of logic cells per clb
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bool split_lc = false; // whether to represent SLICE as a single bel or separate lut+ff (latter important if ff and
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// lut can be used separately)
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// ** LUT config
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unsigned lut_k = 4; // base number of inputs for lookup table
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enum LutType
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{
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SINGLE_LUT,
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// ...
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} lut_type = LutType::SINGLE_LUT; // different types of fracturable LUT structure
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enum LutCascade
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{
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NO_CASCADE,
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// ...
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} lut_casc = LutCascade::NO_CASCADE; // different types of cascading between LUTs
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// TODO: other features we might want to represent...
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// TODO: fracLUT/FF/mux/carry output sharing matrices
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// ** Carry config
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enum CarryType
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{
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NO_CARRY, // no carry chain
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HA_PRE_LUT, // half addder before LUT (classic fabulous LC)
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PG_POST_LUT, // prop/gen logic after a fractured LUT
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FA_POST_LUT, // full adder after a fractured LUT
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} carry_type = CarryType::HA_PRE_LUT;
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int carry_lut_frac = -1; // how the LUT is fractured for PG_POST_LUT/FA_POST_LUT, if the LUT fracturing is different
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// (or only supported) for carry modes and not in general
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// ** FF config
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unsigned ff_per_lc = 1; // number of flipflops per logic cell
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uint32_t dedi_ff_input = 0; // mask of flipflops in a LC that have dedicated inputs
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uint32_t dedi_ff_output = 0; // mask of flipflops in a LC that have dedicated outputs
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ControlSetConfig clk, sr, en; // flipflop control set routing
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};
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struct FabricConfig
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{
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LogicConfig clb;
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// DSP cascading, BRAM, IP rules, IO, clocking ...
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};
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NEXTPNR_NAMESPACE_END
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#endif
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