39 lines
581 B
Verilog
39 lines
581 B
Verilog
`timescale 1ns / 1ps
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module blinky_tb;
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reg clk = 1'b0, rst = 1'b0;
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reg [7:0] ctr_gold = 8'h00;
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wire [7:0] ctr_gate;
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top dut_i(.clk(clk), .rst(rst), .leds(ctr_gate));
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task oneclk;
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begin
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clk = 1'b1;
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#10;
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clk = 1'b0;
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#10;
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end
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endtask
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initial begin
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$dumpfile("blinky_simtest.vcd");
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$dumpvars(0, blinky_tb);
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#100;
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rst = 1'b1;
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repeat (5) oneclk;
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#5
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rst = 1'b0;
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#5
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repeat (500) begin
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if (ctr_gold !== ctr_gate) begin
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$display("mismatch gold=%b gate=%b", ctr_gold, ctr_gate);
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$stop;
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end
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oneclk;
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ctr_gold = ctr_gold + 1'b1;
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end
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$finish;
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end
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endmodule
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