445 lines
20 KiB
C++
445 lines
20 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 David Shah <david@symbioticeda.com>
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* Copyright (C) 2018 Eddie Hung <eddieh@ece.ubc.ca>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "timing.h"
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#include <algorithm>
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#include <boost/range/adaptor/reversed.hpp>
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#include <deque>
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#include <unordered_map>
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#include <utility>
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#include "log.h"
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#include "util.h"
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NEXTPNR_NAMESPACE_BEGIN
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typedef std::vector<const PortRef *> PortRefVector;
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typedef std::map<int, unsigned> DelayFrequency;
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struct Timing
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{
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Context *ctx;
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bool net_delays;
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bool update;
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delay_t min_slack;
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PortRefVector *crit_path;
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DelayFrequency *slack_histogram;
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struct TimingData
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{
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TimingData() : max_arrival(), max_path_length(), min_remaining_budget() {}
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TimingData(delay_t max_arrival) : max_arrival(max_arrival), max_path_length(), min_remaining_budget() {}
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delay_t max_arrival;
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unsigned max_path_length = 0;
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delay_t min_remaining_budget;
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bool false_startpoint = false;
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};
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Timing(Context *ctx, bool net_delays, bool update, PortRefVector *crit_path = nullptr,
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DelayFrequency *slack_histogram = nullptr)
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: ctx(ctx), net_delays(net_delays), update(update), min_slack(1.0e12 / ctx->target_freq),
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crit_path(crit_path), slack_histogram(slack_histogram)
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{
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}
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delay_t walk_paths()
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{
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const auto clk_period = delay_t(1.0e12 / ctx->target_freq);
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// First, compute the topographical order of nets to walk through the circuit, assuming it is a _acyclic_ graph
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// TODO(eddieh): Handle the case where it is cyclic, e.g. combinatorial loops
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std::vector<NetInfo *> topographical_order;
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std::unordered_map<const NetInfo *, TimingData> net_data;
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// In lieu of deleting edges from the graph, simply count the number of fanins to each output port
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std::unordered_map<const PortInfo *, unsigned> port_fanin;
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std::vector<IdString> input_ports;
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std::vector<const PortInfo *> output_ports;
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for (auto &cell : ctx->cells) {
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input_ports.clear();
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output_ports.clear();
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for (auto &port : cell.second->ports) {
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if (!port.second.net)
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continue;
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if (port.second.type == PORT_OUT)
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output_ports.push_back(&port.second);
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else
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input_ports.push_back(port.first);
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}
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for (auto o : output_ports) {
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IdString clockPort;
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TimingPortClass portClass = ctx->getPortTimingClass(cell.second.get(), o->name, clockPort);
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// If output port is influenced by a clock (e.g. FF output) then add it to the ordering as a timing
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// start-point
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if (portClass == TMG_REGISTER_OUTPUT) {
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DelayInfo clkToQ;
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ctx->getCellDelay(cell.second.get(), clockPort, o->name, clkToQ);
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topographical_order.emplace_back(o->net);
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net_data.emplace(o->net, TimingData{clkToQ.maxDelay()});
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} else {
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if (portClass == TMG_STARTPOINT || portClass == TMG_GEN_CLOCK || portClass == TMG_IGNORE) {
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topographical_order.emplace_back(o->net);
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TimingData td;
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td.false_startpoint = (portClass == TMG_GEN_CLOCK || portClass == TMG_IGNORE);
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net_data.emplace(o->net, std::move(td));
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}
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// Otherwise, for all driven input ports on this cell, if a timing arc exists between the input and
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// the current output port, increment fanin counter
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for (auto i : input_ports) {
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DelayInfo comb_delay;
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bool is_path = ctx->getCellDelay(cell.second.get(), i, o->name, comb_delay);
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if (is_path)
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port_fanin[o]++;
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}
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}
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}
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}
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std::deque<NetInfo *> queue(topographical_order.begin(), topographical_order.end());
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// Now walk the design, from the start points identified previously, building up a topographical order
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while (!queue.empty()) {
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const auto net = queue.front();
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queue.pop_front();
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for (auto &usr : net->users) {
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IdString clockPort;
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TimingPortClass usrClass = ctx->getPortTimingClass(usr.cell, usr.port, clockPort);
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if (usrClass == TMG_IGNORE || usrClass == TMG_CLOCK_INPUT)
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continue;
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for (auto &port : usr.cell->ports) {
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if (port.second.type != PORT_OUT || !port.second.net)
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continue;
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TimingPortClass portClass = ctx->getPortTimingClass(usr.cell, port.first, clockPort);
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// Skip if this is a clocked output (but allow non-clocked ones)
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if (portClass == TMG_REGISTER_OUTPUT || portClass == TMG_STARTPOINT || portClass == TMG_IGNORE ||
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portClass == TMG_GEN_CLOCK)
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continue;
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DelayInfo comb_delay;
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bool is_path = ctx->getCellDelay(usr.cell, usr.port, port.first, comb_delay);
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if (!is_path)
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continue;
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// Decrement the fanin count, and only add to topographical order if all its fanins have already
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// been visited
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auto it = port_fanin.find(&port.second);
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NPNR_ASSERT(it != port_fanin.end());
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if (--it->second == 0) {
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topographical_order.emplace_back(port.second.net);
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queue.emplace_back(port.second.net);
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port_fanin.erase(it);
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}
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}
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}
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}
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// Sanity check to ensure that all ports where fanins were recorded were indeed visited
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if (!port_fanin.empty()) {
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for (auto fanin : port_fanin) {
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NetInfo *net = fanin.first->net;
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if (net != nullptr) {
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log_info(" remaining fanin includes %s (net %s)\n", fanin.first->name.c_str(ctx),
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net->name.c_str(ctx));
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if (net->driver.cell != nullptr)
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log_info(" driver = %s.%s\n", net->driver.cell->name.c_str(ctx),
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net->driver.port.c_str(ctx));
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for (auto net_user : net->users)
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log_info(" user: %s.%s\n", net_user.cell->name.c_str(ctx), net_user.port.c_str(ctx));
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} else {
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log_info(" remaining fanin includes %s (no net)\n", fanin.first->name.c_str(ctx));
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}
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}
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}
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NPNR_ASSERT(port_fanin.empty());
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// Go forwards topographically to find the maximum arrival time and max path length for each net
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for (auto net : topographical_order) {
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auto &nd = net_data.at(net);
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const auto net_arrival = nd.max_arrival;
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const auto net_length_plus_one = nd.max_path_length + 1;
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nd.min_remaining_budget = clk_period;
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for (auto &usr : net->users) {
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IdString clockPort;
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TimingPortClass portClass = ctx->getPortTimingClass(usr.cell, usr.port, clockPort);
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if (portClass == TMG_REGISTER_INPUT || portClass == TMG_ENDPOINT || portClass == TMG_IGNORE) {
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} else {
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auto net_delay = net_delays ? ctx->getNetinfoRouteDelay(net, usr) : delay_t();
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auto budget_override = ctx->getBudgetOverride(net, usr, net_delay);
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auto usr_arrival = net_arrival + net_delay;
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// Iterate over all output ports on the same cell as the sink
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for (auto port : usr.cell->ports) {
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if (port.second.type != PORT_OUT || !port.second.net)
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continue;
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DelayInfo comb_delay;
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// Look up delay through this path
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bool is_path = ctx->getCellDelay(usr.cell, usr.port, port.first, comb_delay);
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if (!is_path)
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continue;
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auto &data = net_data[port.second.net];
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auto &arrival = data.max_arrival;
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arrival = std::max(arrival, usr_arrival + comb_delay.maxDelay());
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if (!budget_override) { // Do not increment path length if budget overriden since it doesn't
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// require a share of the slack
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auto &path_length = data.max_path_length;
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path_length = std::max(path_length, net_length_plus_one);
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}
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}
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}
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}
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}
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const NetInfo *crit_net = nullptr;
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// Now go backwards topographically to determine the minimum path slack, and to distribute all path slack evenly
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// between all nets on the path
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for (auto net : boost::adaptors::reverse(topographical_order)) {
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auto &nd = net_data.at(net);
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// Ignore false startpoints
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if (nd.false_startpoint) continue;
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const delay_t net_length_plus_one = nd.max_path_length + 1;
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auto &net_min_remaining_budget = nd.min_remaining_budget;
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for (auto &usr : net->users) {
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auto net_delay = net_delays ? ctx->getNetinfoRouteDelay(net, usr) : delay_t();
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auto budget_override = ctx->getBudgetOverride(net, usr, net_delay);
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IdString associatedClock;
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TimingPortClass portClass = ctx->getPortTimingClass(usr.cell, usr.port, associatedClock);
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if (portClass == TMG_REGISTER_INPUT || portClass == TMG_ENDPOINT) {
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const auto net_arrival = nd.max_arrival;
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auto path_budget = clk_period - (net_arrival + net_delay);
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if (update) {
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auto budget_share = budget_override ? 0 : path_budget / net_length_plus_one;
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usr.budget = std::min(usr.budget, net_delay + budget_share);
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net_min_remaining_budget = std::min(net_min_remaining_budget, path_budget - budget_share);
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}
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if (path_budget < min_slack) {
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min_slack = path_budget;
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if (crit_path) {
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crit_path->clear();
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crit_path->push_back(&usr);
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crit_net = net;
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}
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}
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if (slack_histogram) {
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int slack_ps = ctx->getDelayNS(path_budget) * 1000;
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(*slack_histogram)[slack_ps]++;
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}
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} else if (update) {
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// Iterate over all output ports on the same cell as the sink
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for (const auto &port : usr.cell->ports) {
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if (port.second.type != PORT_OUT || !port.second.net)
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continue;
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DelayInfo comb_delay;
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bool is_path = ctx->getCellDelay(usr.cell, usr.port, port.first, comb_delay);
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if (!is_path)
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continue;
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auto path_budget = net_data.at(port.second.net).min_remaining_budget;
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auto budget_share = budget_override ? 0 : path_budget / net_length_plus_one;
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usr.budget = std::min(usr.budget, net_delay + budget_share);
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net_min_remaining_budget = std::min(net_min_remaining_budget, path_budget - budget_share);
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}
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}
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}
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}
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if (crit_path) {
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// Walk backwards from the most critical net
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while (crit_net) {
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const PortInfo *crit_ipin = nullptr;
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delay_t max_arrival = std::numeric_limits<delay_t>::min();
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// Look at all input ports on its driving cell
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for (const auto &port : crit_net->driver.cell->ports) {
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if (port.second.type != PORT_IN || !port.second.net)
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continue;
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DelayInfo comb_delay;
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bool is_path =
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ctx->getCellDelay(crit_net->driver.cell, port.first, crit_net->driver.port, comb_delay);
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if (!is_path)
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continue;
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// If input port is influenced by a clock, skip
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IdString portClock;
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TimingPortClass portClass = ctx->getPortTimingClass(crit_net->driver.cell, port.first, portClock);
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if (portClass == TMG_REGISTER_INPUT || portClass == TMG_CLOCK_INPUT || portClass == TMG_ENDPOINT ||
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portClass == TMG_IGNORE)
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continue;
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// And find the fanin net with the latest arrival time
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const auto net_arrival = net_data.at(port.second.net).max_arrival;
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if (net_arrival > max_arrival) {
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max_arrival = net_arrival;
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crit_ipin = &port.second;
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}
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}
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if (!crit_ipin)
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break;
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// Now convert PortInfo* into a PortRef*
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for (auto &usr : crit_ipin->net->users) {
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if (usr.cell->name == crit_net->driver.cell->name && usr.port == crit_ipin->name) {
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crit_path->push_back(&usr);
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break;
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}
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}
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crit_net = crit_ipin->net;
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}
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std::reverse(crit_path->begin(), crit_path->end());
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}
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return min_slack;
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}
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void assign_budget()
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{
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// Clear delays to a very high value first
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for (auto &net : ctx->nets) {
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for (auto &usr : net.second->users) {
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usr.budget = std::numeric_limits<delay_t>::max();
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}
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}
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walk_paths();
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}
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};
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void assign_budget(Context *ctx, bool quiet)
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{
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if (!quiet) {
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log_break();
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log_info("Annotating ports with timing budgets for target frequency %.2f MHz\n", ctx->target_freq / 1e6);
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}
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Timing timing(ctx, ctx->slack_redist_iter > 0 /* net_delays */, true /* update */);
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timing.assign_budget();
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if (!quiet || ctx->verbose) {
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for (auto &net : ctx->nets) {
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for (auto &user : net.second->users) {
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// Post-update check
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if (!ctx->auto_freq && user.budget < 0)
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log_warning("port %s.%s, connected to net '%s', has negative "
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"timing budget of %fns\n",
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user.cell->name.c_str(ctx), user.port.c_str(ctx), net.first.c_str(ctx),
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ctx->getDelayNS(user.budget));
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else if (ctx->verbose)
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log_info("port %s.%s, connected to net '%s', has "
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"timing budget of %fns\n",
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user.cell->name.c_str(ctx), user.port.c_str(ctx), net.first.c_str(ctx),
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ctx->getDelayNS(user.budget));
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}
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}
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}
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// For slack redistribution, if user has not specified a frequency dynamically adjust the target frequency to be the
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// currently achieved maximum
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if (ctx->auto_freq && ctx->slack_redist_iter > 0) {
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delay_t default_slack = delay_t((1.0e9 / ctx->getDelayNS(1)) / ctx->target_freq);
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ctx->target_freq = 1.0e9 / ctx->getDelayNS(default_slack - timing.min_slack);
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if (ctx->verbose)
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log_info("minimum slack for this assign = %.2f ns, target Fmax for next "
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"update = %.2f MHz\n",
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ctx->getDelayNS(timing.min_slack), ctx->target_freq / 1e6);
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}
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if (!quiet)
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log_info("Checksum: 0x%08x\n", ctx->checksum());
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}
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void timing_analysis(Context *ctx, bool print_histogram, bool print_path)
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{
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PortRefVector crit_path;
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DelayFrequency slack_histogram;
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Timing timing(ctx, true /* net_delays */, false /* update */, print_path ? &crit_path : nullptr,
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print_histogram ? &slack_histogram : nullptr);
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auto min_slack = timing.walk_paths();
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if (print_path) {
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if (crit_path.empty()) {
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log_info("Design contains no timing paths\n");
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} else {
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delay_t total = 0;
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log_break();
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log_info("Critical path report:\n");
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log_info("curr total\n");
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auto &front = crit_path.front();
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auto &front_port = front->cell->ports.at(front->port);
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auto &front_driver = front_port.net->driver;
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IdString last_port;
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ctx->getPortTimingClass(front_driver.cell, front_driver.port, last_port);
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for (auto sink : crit_path) {
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auto sink_cell = sink->cell;
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auto &port = sink_cell->ports.at(sink->port);
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auto net = port.net;
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auto &driver = net->driver;
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auto driver_cell = driver.cell;
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DelayInfo comb_delay;
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ctx->getCellDelay(sink_cell, last_port, driver.port, comb_delay);
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total += comb_delay.maxDelay();
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log_info("%4.1f %4.1f Source %s.%s\n", ctx->getDelayNS(comb_delay.maxDelay()), ctx->getDelayNS(total),
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driver_cell->name.c_str(ctx), driver.port.c_str(ctx));
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auto net_delay = ctx->getNetinfoRouteDelay(net, *sink);
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total += net_delay;
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auto driver_loc = ctx->getBelLocation(driver_cell->bel);
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auto sink_loc = ctx->getBelLocation(sink_cell->bel);
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log_info("%4.1f %4.1f Net %s budget %f ns (%d,%d) -> (%d,%d)\n", ctx->getDelayNS(net_delay),
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ctx->getDelayNS(total), net->name.c_str(ctx), ctx->getDelayNS(sink->budget), driver_loc.x,
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driver_loc.y, sink_loc.x, sink_loc.y);
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log_info(" Sink %s.%s\n", sink_cell->name.c_str(ctx), sink->port.c_str(ctx));
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last_port = sink->port;
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}
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log_break();
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}
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}
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delay_t default_slack = delay_t((1.0e9 / ctx->getDelayNS(1)) / ctx->target_freq);
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log_info("estimated Fmax = %.2f MHz\n", 1e3 / ctx->getDelayNS(default_slack - min_slack));
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if (print_histogram && slack_histogram.size() > 0) {
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unsigned num_bins = 20;
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unsigned bar_width = 60;
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auto min_slack = slack_histogram.begin()->first;
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auto max_slack = slack_histogram.rbegin()->first;
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auto bin_size = std::max(1u, (max_slack - min_slack) / num_bins);
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num_bins = std::min((max_slack - min_slack) / bin_size, num_bins) + 1;
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std::vector<unsigned> bins(num_bins);
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unsigned max_freq = 0;
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for (const auto &i : slack_histogram) {
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auto &bin = bins[(i.first - min_slack) / bin_size];
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bin += i.second;
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max_freq = std::max(max_freq, bin);
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}
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bar_width = std::min(bar_width, max_freq);
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log_break();
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log_info("Slack histogram:\n");
|
|
log_info(" legend: * represents %d endpoint(s)\n", max_freq / bar_width);
|
|
log_info(" + represents [1,%d) endpoint(s)\n", max_freq / bar_width);
|
|
for (unsigned i = 0; i < num_bins; ++i)
|
|
log_info("[%6d, %6d) |%s%c\n", min_slack + bin_size * i, min_slack + bin_size * (i + 1),
|
|
std::string(bins[i] * bar_width / max_freq, '*').c_str(),
|
|
(bins[i] * bar_width) % max_freq > 0 ? '+' : ' ');
|
|
}
|
|
}
|
|
|
|
NEXTPNR_NAMESPACE_END
|