ff7b8535bc
* Gowin. Add DHCEN primitive. This primitive allows you to dynamically turn off and turn on the networks of high-speed clocks. This is done tracking the routes to the sinks and if the route passes through a special HCLK MUX (this may be the input MUX or the output MUX, as well as the interbank MUX), then the control signal of this MUX is used. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> * Gowin. Change the DHCEN binding Use the entire PIP instead of a wire - avoids normalisation and may also be useful in the future when calculating clock stuff. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> --------- Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
452 lines
16 KiB
C++
452 lines
16 KiB
C++
#include "log.h"
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#include "nextpnr.h"
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#include "util.h"
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#define HIMBAECHEL_CONSTIDS "uarch/gowin/constids.inc"
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#include "himbaechel_constids.h"
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#include "himbaechel_helpers.h"
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#include <queue>
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#include "gowin.h"
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#include "gowin_utils.h"
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NEXTPNR_NAMESPACE_BEGIN
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// tile extra data
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IdString GowinUtils::get_tile_class(int x, int y)
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{
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int tile = tile_by_xy(ctx->chip_info, x, y);
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const Tile_extra_data_POD *extra =
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reinterpret_cast<const Tile_extra_data_POD *>(chip_tile_info(ctx->chip_info, tile).extra_data.get());
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return IdString(extra->class_id);
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}
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// oser16/ides16 aux cell offsets
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Loc GowinUtils::get_tile_io16_offs(int x, int y)
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{
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int tile = tile_by_xy(ctx->chip_info, x, y);
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const Tile_extra_data_POD *extra =
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reinterpret_cast<const Tile_extra_data_POD *>(chip_tile_info(ctx->chip_info, tile).extra_data.get());
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return Loc(extra->io16_x_off, extra->io16_y_off, 0);
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}
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// pin functions: GCLKT_4, SSPI_CS, READY etc
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IdStringList GowinUtils::get_pin_funcs(BelId io_bel)
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{
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IdStringList bel_name = ctx->getBelName(io_bel);
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const PadInfoPOD *pins = ctx->package_info->pads.get();
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size_t len = ctx->package_info->pads.ssize();
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for (size_t i = 0; i < len; i++) {
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const PadInfoPOD *pin = &pins[i];
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if (IdString(pin->tile) == bel_name[0] && IdString(pin->bel) == bel_name[1]) {
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return IdStringList::parse(ctx, IdString(pin->pad_function).str(ctx));
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}
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}
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return IdStringList();
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}
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// PLL pads
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BelId GowinUtils::get_pll_bel(BelId io_bel, IdString type)
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{
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IdStringList bel_name = ctx->getBelName(io_bel);
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const PadInfoPOD *pins = ctx->package_info->pads.get();
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size_t len = ctx->package_info->pads.ssize();
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for (size_t i = 0; i < len; i++) {
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const PadInfoPOD *pin = &pins[i];
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if (IdString(pin->tile) == bel_name[0] && IdString(pin->bel) == bel_name[1]) {
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const Pad_extra_data_POD *extra = reinterpret_cast<const Pad_extra_data_POD *>(pin->extra_data.get());
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if (extra != nullptr && IdString(extra->pll_type) == type) {
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return ctx->getBelByName(IdStringList::concat(IdString(extra->pll_tile), IdString(extra->pll_bel)));
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}
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}
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}
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return BelId();
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}
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BelId GowinUtils::get_dqce_bel(IdString spine_name)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
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for (auto &spine_bel : extra->dqce_bels) {
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if (IdString(spine_bel.spine) == spine_name) {
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return ctx->getBelByLocation(Loc(spine_bel.bel_x, spine_bel.bel_y, spine_bel.bel_z));
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}
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}
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return BelId();
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}
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BelId GowinUtils::get_dcs_bel(IdString spine_name)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
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for (auto &spine_bel : extra->dcs_bels) {
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if (IdString(spine_bel.spine) == spine_name) {
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return ctx->getBelByLocation(Loc(spine_bel.bel_x, spine_bel.bel_y, spine_bel.bel_z));
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}
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}
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return BelId();
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}
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BelId GowinUtils::get_dhcen_bel(WireId hclkin_wire, IdString &side)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
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for (auto &wire_bel : extra->dhcen_bels) {
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IdString dst = IdString(wire_bel.pip_dst);
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IdString src = IdString(wire_bel.pip_src);
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IdStringList pip = IdStringList::concat(IdStringList::concat(IdString(wire_bel.pip_xy), dst), src);
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WireId wire = ctx->getPipDstWire(ctx->getPipByName(pip));
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if (wire == hclkin_wire) {
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side = IdString(wire_bel.side);
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return ctx->getBelByLocation(Loc(wire_bel.bel_x, wire_bel.bel_y, wire_bel.bel_z));
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}
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}
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return BelId();
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}
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bool GowinUtils::is_simple_io_bel(BelId bel)
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{
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return chip_bel_info(ctx->chip_info, bel).flags & BelFlags::FLAG_SIMPLE_IO;
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}
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Loc GowinUtils::get_pair_iologic_bel(Loc loc)
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{
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int const z[] = {1, 0, 3, 2};
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loc.z = BelZ::IOLOGICA_Z + z[(loc.z - BelZ::IOLOGICA_Z)];
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return loc;
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}
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BelId GowinUtils::get_io_bel_from_iologic(BelId bel)
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{
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Loc loc = ctx->getBelLocation(bel);
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loc.z = BelZ::IOBA_Z + ((loc.z - BelZ::IOLOGICA_Z) & 1);
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return ctx->getBelByLocation(loc);
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}
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bool GowinUtils::is_diff_io_supported(IdString type)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
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for (auto &dtype : extra->diff_io_types) {
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if (IdString(dtype) == type) {
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return true;
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}
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}
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return false;
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}
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bool GowinUtils::has_bottom_io_cnds(void)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
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return extra->bottom_io.conditions.size() != 0;
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}
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IdString GowinUtils::get_bottom_io_wire_a_net(int8_t condition)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
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return IdString(extra->bottom_io.conditions[condition].wire_a_net);
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}
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IdString GowinUtils::get_bottom_io_wire_b_net(int8_t condition)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
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return IdString(extra->bottom_io.conditions[condition].wire_b_net);
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}
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bool GowinUtils::has_BANDGAP(void)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
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return extra->chip_flags & Extra_chip_data_POD::HAS_BANDGAP;
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}
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bool GowinUtils::has_SP32(void)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
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return extra->chip_flags & Extra_chip_data_POD::HAS_SP32;
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}
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bool GowinUtils::need_SP_fix(void)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
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return extra->chip_flags & Extra_chip_data_POD::NEED_SP_FIX;
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}
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bool GowinUtils::need_BSRAM_OUTREG_fix(void)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
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return extra->chip_flags & Extra_chip_data_POD::NEED_BSRAM_OUTREG_FIX;
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}
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bool GowinUtils::need_BLKSEL_fix(void)
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{
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const Extra_chip_data_POD *extra = reinterpret_cast<const Extra_chip_data_POD *>(ctx->chip_info->extra_data.get());
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return extra->chip_flags & Extra_chip_data_POD::NEED_BLKSEL_FIX;
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}
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std::unique_ptr<CellInfo> GowinUtils::create_cell(IdString name, IdString type)
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{
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NPNR_ASSERT(!ctx->cells.count(name));
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return std::make_unique<CellInfo>(ctx, name, type);
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}
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// DSP
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Loc GowinUtils::get_dsp_next_9_in_chain(Loc from) const
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{
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Loc res;
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res.y = from.y;
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if (get_dsp_18_idx(from.z) == 0) {
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res.x = from.x;
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res.z = from.z + 4;
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return res;
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}
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if (get_dsp_macro_num(from.z)) {
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// next DSP
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res.x = from.x + 9;
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res.z = from.z & (~0x24);
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} else {
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// next macro
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res.x = from.x;
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res.z = get_dsp_next_macro(from.z) & (~4);
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}
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return res;
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}
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Loc GowinUtils::get_dsp_next_macro_in_chain(Loc from) const
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{
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Loc res;
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res.y = from.y;
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if (get_dsp_macro_num(from.z)) {
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// next DSP
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res.x = from.x + 9;
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res.z = from.z & (~0x20);
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} else {
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// next macro
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res.x = from.x;
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res.z = get_dsp_next_macro(from.z);
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}
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return res;
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}
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Loc GowinUtils::get_dsp_next_in_chain(Loc from, IdString dsp_type) const
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{
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if (dsp_type.in(id_PADD9, id_PADD18, id_MULT9X9, id_MULT18X18)) {
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return get_dsp_next_9_in_chain(from);
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}
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if (dsp_type.in(id_ALU54D, id_MULTALU18X18, id_MULTALU36X18, id_MULTADDALU18X18)) {
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return get_dsp_next_macro_in_chain(from);
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}
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NPNR_ASSERT_FALSE("Unknown DSP cell type.");
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}
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CellInfo *GowinUtils::dsp_bus_src(const CellInfo *ci, const char *bus_prefix, int wire_num) const
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{
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bool connected_to_const = false; // and disconnected too
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CellInfo *connected_to_cell = nullptr;
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for (int i = 0; i < wire_num; ++i) {
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const NetInfo *net = ci->getPort(ctx->idf("%s[%d]", bus_prefix, i));
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if (connected_to_cell == nullptr) {
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if (net == nullptr || net->driver.cell == nullptr || net->name == ctx->id("$PACKER_VCC") ||
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net->name == ctx->id("$PACKER_GND")) {
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connected_to_const = true;
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continue;
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} else {
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if (connected_to_const) {
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log_error("The %s cell %s bus is connected simultaneously to constants and to another DSP.\n",
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ctx->nameOf(ci), bus_prefix);
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}
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}
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}
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if (net == nullptr || !is_dsp(net->driver.cell)) {
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log_error("The %s cell %s bus is not connected to another DSP.\n", ctx->nameOf(ci), bus_prefix);
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}
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if (connected_to_cell != nullptr && net->driver.cell != connected_to_cell) {
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log_error("The %s cell %s bus is connected to different DSPs: %s and %s.\n", ctx->nameOf(ci), bus_prefix,
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ctx->nameOf(connected_to_cell), ctx->nameOf(net->driver.cell));
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}
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connected_to_cell = net->driver.cell;
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}
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if (connected_to_const) {
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return nullptr;
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}
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return connected_to_cell;
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}
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CellInfo *GowinUtils::dsp_bus_dst(const CellInfo *ci, const char *bus_prefix, int wire_num) const
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{
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bool disconnected = false; // and disconnected too
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CellInfo *connected_to_cell = nullptr;
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for (int i = 0; i < wire_num; ++i) {
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const NetInfo *net = ci->getPort(ctx->idf("%s[%d]", bus_prefix, i));
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if (connected_to_cell == nullptr) {
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if (net == nullptr || net->users.entries() == 0) {
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disconnected = true;
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continue;
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} else {
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if (disconnected) {
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log_error("The %s cell %s bus is partially disconnected.\n", ctx->nameOf(ci), bus_prefix);
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}
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}
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}
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if (net->users.entries() > 1) {
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log_error("Net %s has >1 users.\n", ctx->nameOf(net));
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}
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CellInfo *dst = (*net->users.begin()).cell;
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if (net == nullptr || !is_dsp(dst)) {
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log_error("The %s cell %s bus is not connected to another DSP.\n", ctx->nameOf(ci), bus_prefix);
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}
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if (connected_to_cell != nullptr && dst != connected_to_cell) {
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log_error("The %s cell %s bus is connected to different DSPs: %s and %s.\n", ctx->nameOf(ci), bus_prefix,
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ctx->nameOf(connected_to_cell), ctx->nameOf(dst));
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}
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connected_to_cell = dst;
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}
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if (disconnected) {
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return nullptr;
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}
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return connected_to_cell;
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}
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// Use the upper CLKDIV as the id for a hclk section
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IdStringList GowinUtils::get_hclk_id(BelId hclk_bel) const
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{
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IdString bel_type = ctx->getBelType(hclk_bel);
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NPNR_ASSERT(hclk_bel != BelId() && bel_type.in(id_CLKDIV2, id_CLKDIV));
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Loc id_loc = Loc(ctx->getBelLocation(hclk_bel));
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if (bel_type == id_CLKDIV) {
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return get_hclk_id(get_clkdiv2_for_clkdiv(hclk_bel));
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} else if (id_loc.z == BelZ::CLKDIV2_0_Z || id_loc.z == BelZ::CLKDIV2_2_Z)
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return ctx->getBelName(hclk_bel);
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else
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return ctx->getBelName(ctx->getBelByLocation(Loc(id_loc.x, id_loc.y, id_loc.z - 1)));
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return IdStringList();
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}
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// Get the clkdiv in the same section as a clkdiv2
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BelId GowinUtils::get_clkdiv_for_clkdiv2(BelId clkdiv2_bel) const
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{
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NPNR_ASSERT(clkdiv2_bel != BelId() && (ctx->getBelType(clkdiv2_bel) == id_CLKDIV2));
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Loc clkdiv_loc = ctx->getBelLocation(clkdiv2_bel);
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clkdiv_loc.z = BelZ::CLKDIV_0_Z + (clkdiv_loc.z - BelZ::CLKDIV2_0_Z);
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return ctx->getBelByLocation(clkdiv_loc);
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}
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// Get the clkdiv2 in the same section as a clkdiv
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BelId GowinUtils::get_clkdiv2_for_clkdiv(BelId clkdiv_bel) const
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{
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NPNR_ASSERT(clkdiv_bel != BelId() && (ctx->getBelType(clkdiv_bel) == id_CLKDIV));
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Loc clkdiv_loc = ctx->getBelLocation(clkdiv_bel);
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Loc clkdiv2_loc = Loc(clkdiv_loc.x, clkdiv_loc.y, BelZ::CLKDIV2_0_Z + (clkdiv_loc.z - BelZ::CLKDIV_0_Z));
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return ctx->getBelByLocation(clkdiv2_loc);
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}
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// Get the clkdiv in the neighbouring section to a clkdiv
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BelId GowinUtils::get_other_hclk_clkdiv(BelId clkdiv_bel) const
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{
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NPNR_ASSERT(clkdiv_bel != BelId() && (ctx->getBelType(clkdiv_bel) == id_CLKDIV));
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Loc other_loc = Loc(ctx->getBelLocation(clkdiv_bel));
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int dz = BelZ::CLKDIV_1_Z - BelZ::CLKDIV_0_Z;
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if (other_loc.z == BelZ::CLKDIV_1_Z || other_loc.z == BelZ::CLKDIV_3_Z)
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dz = -dz;
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other_loc.z += dz;
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return ctx->getBelByLocation(other_loc);
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}
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// Get the clkdiv2 in the neighbouring section to a clkdiv2
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BelId GowinUtils::get_other_hclk_clkdiv2(BelId clkdiv2_bel) const
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{
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NPNR_ASSERT(clkdiv2_bel != BelId() && (ctx->getBelType(clkdiv2_bel) == id_CLKDIV2));
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Loc other_loc = Loc(ctx->getBelLocation(clkdiv2_bel));
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int dz = BelZ::CLKDIV2_1_Z - BelZ::CLKDIV2_0_Z;
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if (other_loc.z == BelZ::CLKDIV2_1_Z || other_loc.z == BelZ::CLKDIV2_3_Z)
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dz = -dz;
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other_loc.z += dz;
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return ctx->getBelByLocation(other_loc);
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}
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// Credit: https://cp-algorithms.com/graph/kuhn_maximum_bipartite_matching.html
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std::vector<int> GowinUtils::kuhn_find_maximum_bipartite_matching(int n, int k, std::vector<std::vector<int>> &g)
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{
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std::vector<int> mt;
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std::vector<bool> used(n);
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auto try_kuhn = [&](int v, auto &try_kuhn_ref) -> bool {
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if (used[v])
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return false;
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used[v] = true;
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for (int to : g[v]) {
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if (mt[to] == -1 || try_kuhn_ref(mt[to], try_kuhn_ref)) {
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mt[to] = v;
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return true;
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}
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}
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return false;
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};
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mt.assign(k, -1);
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for (int v = 0; v < n; ++v) {
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used.assign(n, false);
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try_kuhn(v, try_kuhn);
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}
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return mt;
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}
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// original implementation: nextpnr/machxo2/pack.cc
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// Using a BFS, search for bels of a given type either upstream or downstream of another cell
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void GowinUtils::find_connected_bels(const CellInfo *cell, IdString port, IdString dest_type, IdString dest_pin,
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int iter_limit, std::vector<BelId> &candidates)
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{
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int iter = 0;
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std::queue<WireId> visit;
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pool<WireId> seen_wires;
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pool<BelId> seen_bels;
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BelId bel = cell->bel;
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if (bel == BelId())
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return;
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WireId start_wire = ctx->getBelPinWire(bel, port);
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NPNR_ASSERT(start_wire != WireId());
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PortType dir = ctx->getBelPinType(bel, port);
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visit.push(start_wire);
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|
|
|
while (!visit.empty() && (iter++ < iter_limit)) {
|
|
WireId cursor = visit.front();
|
|
visit.pop();
|
|
// Check to see if we have reached a valid bel pin
|
|
for (auto bp : ctx->getWireBelPins(cursor)) {
|
|
if (ctx->getBelType(bp.bel) != dest_type)
|
|
continue;
|
|
if (dest_pin != IdString() && bp.pin != dest_pin)
|
|
continue;
|
|
if (seen_bels.count(bp.bel))
|
|
continue;
|
|
seen_bels.insert(bp.bel);
|
|
candidates.push_back(bp.bel);
|
|
}
|
|
// Search in the appropriate direction up/downstream of the cursor
|
|
if (dir == PORT_OUT) {
|
|
for (PipId p : ctx->getPipsDownhill(cursor))
|
|
if (ctx->checkPipAvail(p)) {
|
|
WireId dst = ctx->getPipDstWire(p);
|
|
if (seen_wires.count(dst))
|
|
continue;
|
|
seen_wires.insert(dst);
|
|
visit.push(dst);
|
|
}
|
|
} else {
|
|
for (PipId p : ctx->getPipsUphill(cursor))
|
|
if (ctx->checkPipAvail(p)) {
|
|
WireId src = ctx->getPipSrcWire(p);
|
|
if (seen_wires.count(src))
|
|
continue;
|
|
seen_wires.insert(src);
|
|
visit.push(src);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
NEXTPNR_NAMESPACE_END
|