492 lines
22 KiB
C++
492 lines
22 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2024 Miodrag Milanovic <micko@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <boost/algorithm/string.hpp>
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#include <boost/range/adaptor/reversed.hpp>
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#include <fstream>
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#include <regex>
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#include "extra_data.h"
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#include "himbaechel_api.h"
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#include "log.h"
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#include "nextpnr.h"
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#include "util.h"
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#include "ng_ultra.h"
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#define HIMBAECHEL_CONSTIDS "uarch/ng-ultra/constids.inc"
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#include "himbaechel_constids.h"
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NEXTPNR_NAMESPACE_BEGIN
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namespace {
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struct BitstreamJsonBackend
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{
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Context *ctx;
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NgUltraImpl *uarch;
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std::ostream &out;
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bool first_instance;
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BitstreamJsonBackend(Context *ctx, NgUltraImpl *uarch, std::ostream &out) : ctx(ctx), uarch(uarch), out(out){};
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std::string get_string(std::string str)
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{
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std::string newstr = "\"";
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for (char c : str) {
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if (c == '\\')
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newstr += c;
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newstr += c;
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}
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return newstr + "\"";
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}
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std::string update_name(std::string tile, std::string name)
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{
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if (boost::starts_with(tile,"FENCE[")) {
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char last = tile[tile.size()-2];
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switch(last)
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{
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case 'T':
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case 'B':
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case 'U':
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case 'L':
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std::string loc = tile.substr(tile.find("[")+1, tile.find("x")-tile.find("["));
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boost::replace_all(name, "1x", loc);
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return name;
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}
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}
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if (boost::starts_with(tile,"TILE[") && boost::algorithm::contains(name,".FE")) {
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std::string last = name.substr(name.rfind('.') + 1);
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if (last[0]=='D') {
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boost::replace_all(name, ".D", ".");
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boost::replace_all(name, ".FE", ".DFF");
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return name;
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}
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if (last=="L" || last=="R") {
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boost::replace_all(name, ".FE", ".DFF");
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return name;
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}
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if (last=="CK") {
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boost::replace_all(name, ".FE", ".DFF");
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return name;
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}
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if (last[0]=='L') {
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boost::replace_all(name, ".L", ".");
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boost::replace_all(name, ".FE", ".LUT");
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return name;
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}
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if (last[0]=='P') {
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boost::replace_all(name, ".PI", ".I");
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boost::replace_all(name, ".FE", ".LUT");
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return name;
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}
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}
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return name;
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}
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void add_net(std::set<std::string> &nets, std::string src_tile, std::string src_name, std::string dst_tile, std::string dst_name, IdString src_type, IdString dst_type)
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{
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if (src_type.in(ctx->id("LUT_PERMUTATION_WIRE"), ctx->id("MUX_WIRE"), ctx->id("INTERCONNECT_INPUT"))) return;
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if (boost::starts_with(src_type.c_str(ctx),"CROSSBAR_") && boost::ends_with(src_type.c_str(ctx),"INPUT_WIRE")) return;
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if (dst_type == ctx->id("MUX_WIRE"))
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dst_name = dst_name.substr(0, dst_name.rfind('.'));
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src_name = update_name(src_tile, src_name);
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dst_name = update_name(dst_tile, dst_name);
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nets.emplace(stringf("%s:%s->%s:%s", src_tile.c_str(), src_name.c_str(), dst_tile.c_str(), dst_name.c_str()));
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}
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std::string cleanup_name(std::string name)
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{
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std::replace(name.begin(), name.end(), '$', '_');
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return name;
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}
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void write_nets()
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{
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out << "\t\"nets\": {\n";
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bool first_net = true;
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for (auto &net : ctx->nets) {
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NetInfo *ni = net.second.get();
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if (ni->wires.size()==0) continue;
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out << (first_net ? "" : ",\n"); first_net = false;
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out << stringf("\t\t%s: [\n", get_string(cleanup_name(ni->name.c_str(ctx))).c_str());
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std::set<std::string> nets;
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for (auto &w : ni->wires) {
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if (w.second.pip != PipId()) {
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PipId pip = w.second.pip;
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auto &pd = chip_pip_info(ctx->chip_info, pip);
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const auto &extra_data = *reinterpret_cast<const NGUltraPipExtraDataPOD *>(pd.extra_data.get());
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WireId swire = ctx->getPipSrcWire(pip);
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IdString src = ctx->getWireName(swire)[1];
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IdString src_type = ctx->getWireType(swire);
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IdString src_orig = IdString(chip_tile_info(ctx->chip_info, pip.tile).wires[pd.src_wire].name);
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IdString src_orig_type = IdString(chip_tile_info(ctx->chip_info, pip.tile).wires[pd.src_wire].wire_type);
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WireId dwire = ctx->getPipDstWire(pip);
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IdString dst = ctx->getWireName(dwire)[1];
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IdString dst_type = ctx->getWireType(dwire);
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std::string s_tile_name = uarch->tile_name(swire.tile);
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std::string tile_name = uarch->tile_name(pip.tile);
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if (src_orig!=src)
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add_net(nets, s_tile_name, src.c_str(ctx), tile_name, src_orig.c_str(ctx), src_type, src_orig_type);
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if (!extra_data.name || (extra_data.type != PipExtra::PIP_EXTRA_BYPASS && extra_data.type != PipExtra::PIP_EXTRA_VIRTUAL && extra_data.type != PipExtra::PIP_EXTRA_MUX))
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add_net(nets, tile_name, src_orig.c_str(ctx), tile_name, dst.c_str(ctx), src_orig_type, dst_type);
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} else if (ni->wires.size()==1) {
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IdString src = ctx->getWireName(w.first)[1];
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IdString src_type = ctx->getWireType(w.first);
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std::string s_tile_name = uarch->tile_name(w.first.tile);
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for (auto &u : ni->users){
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std::string tile_name = uarch->tile_name(u.cell->bel.tile);
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IdString bel_name = ctx->getBelName(u.cell->bel)[1];
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add_net(nets, s_tile_name, src.c_str(ctx), tile_name, stringf("%s.%s", bel_name.c_str(ctx), u.port.c_str(ctx)), src_type, src_type);
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}
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}
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}
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bool first = true;
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for (auto &str : nets) {
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out << (first ? "" : ",\n");
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out << stringf("\t\t\t%s",get_string(str).c_str());
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first = false;
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}
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out << "\n\t\t]";
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}
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out << "\n\t},\n";
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}
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template <typename KeyType>
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std::string str_or_n_value(const dict<KeyType, Property> &ct, const KeyType &key, std::string def = "N")
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{
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auto found = ct.find(key);
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if (found == ct.end())
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return def;
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else {
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if (!found->second.is_string)
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log_error("Expecting string value but got integer %d.\n", int(found->second.intval));
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if (found->second.as_string().empty())
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return def;
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return found->second.as_string();
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}
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};
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template <typename KeyType> std::string extract_bits_or_default(const dict<KeyType, Property> &ct, const KeyType &key, int bits, int def = 0)
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{
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Property extr = get_or_default(ct, key, Property()).extract(0, bits);
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std::string str = extr.str;
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std::reverse(str.begin(), str.end());
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return str;
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};
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std::vector<std::string> config;
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void open_instance(CellInfo *cell, std::string rename = "")
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{
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out << stringf("%s", first_instance ? "" : ",\n"); first_instance = false;
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out << stringf("\t\t%s: {\n", get_string(cleanup_name(rename.empty() ? cell->name.c_str(ctx) : rename.c_str())).c_str());
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std::string tile_name = uarch->tile_name(cell->bel.tile);
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IdString idx = ctx->getBelName(cell->bel)[1];
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std::string belname = idx.c_str(ctx);
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config.clear();
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out << stringf("\t\t\t\"location\": %s,\n",get_string(tile_name + ":" + belname).c_str());
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out << stringf("\t\t\t\"type\": %s",get_string(cell->type.c_str(ctx)).c_str());
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}
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void open_instance_fe(CellInfo *cell, std::string type, std::string replace, std::string postfix = "")
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{
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out << stringf("%s", first_instance ? "" : ",\n"); first_instance = false;
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out << stringf("\t\t%s: {\n", get_string(cleanup_name(cell->name.c_str(ctx)) + postfix).c_str());
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std::string tile_name = uarch->tile_name(cell->bel.tile);
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IdString idx = ctx->getBelName(cell->bel)[1];
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std::string belname = idx.c_str(ctx);
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boost::replace_all(belname, ".FE", replace);
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config.clear();
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out << stringf("\t\t\t\"location\": %s,\n",get_string(tile_name + ":" + belname).c_str());
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out << stringf("\t\t\t\"type\": %s",get_string(type).c_str());
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}
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inline void add_config(std::string name, int val)
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{
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config.push_back(stringf("\t\t\t\t%s:%d", get_string(name).c_str(), val));
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}
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inline void add_config(std::string name, bool val)
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{
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config.push_back(stringf("\t\t\t\t%s:%s", get_string(name).c_str(), val ? "true" : "false"));
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}
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inline void add_config(std::string name, std::string val)
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{
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config.push_back(stringf("\t\t\t\t%s:%s", get_string(name).c_str(), get_string(val).c_str()));
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}
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void close_instance() {
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bool first = true;
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if (!config.empty()) out << ",\n\t\t\t\"config\": {\n";
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for (auto &str : config) {
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out << (first ? "" : ",\n");
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out << str.c_str();
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first = false;
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}
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if (!config.empty()) out << "\n\t\t\t}";
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out << "\n\t\t}";
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config.clear();
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}
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void write_iop(CellInfo *cell) {
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open_instance(cell, str_or_default(cell->params, ctx->id("iobname"), ""));
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//add_config("alias_vhdl", str_or_default(cell->params, ctx->id("alias_vhdl"), ""));
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//add_config("alias_vlog", str_or_default(cell->params, ctx->id("alias_vlog"), ""));
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//add_config("differential", str_or_n_value(cell->params, ctx->id("differential"), "N"));
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add_config("drive", str_or_default(cell->params, ctx->id("drive"), "2mA"));
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//add_config("dynDrive", str_or_n_value(cell->params, ctx->id("dynDrive"), "N"));
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//add_config("dynInput", str_or_n_value(cell->params, ctx->id("dynInput"), "N"));
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//add_config("dynTerm", str_or_n_value(cell->params, ctx->id("dynTerm"), "N"));
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//add_config("extra", int_or_default(cell->params, ctx->id("extra"), 2));
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//add_config("inputDelayLine", str_or_default(cell->params, ctx->id("inputDelayLine"), ""));
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//add_config("inputDelayOn", str_or_n_value(cell->params, ctx->id("inputDelayOn"), "N"));
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//add_config("inputSignalSlope", str_or_default(cell->params, ctx->id("inputSignalSlope"), ""));
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add_config("location", str_or_default(cell->params, ctx->id("location"), ""));
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//add_config("locked", bool_or_default(cell->params, ctx->id("locked"), false));
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//add_config("outputCapacity", str_or_default(cell->params, ctx->id("outputCapacity"), ""));
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//add_config("outputDelayLine", str_or_default(cell->params, ctx->id("outputDelayLine"), ""));
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//add_config("outputDelayOn", str_or_n_value(cell->params, ctx->id("outputDelayOn"), "N"));
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//add_config("slewRate", str_or_default(cell->params, ctx->id("slewRate"), ""));
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add_config("standard", str_or_default(cell->params, ctx->id("standard"), "LVCMOS"));
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//add_config("termination", str_or_n_value(cell->params, ctx->id("termination"), "N"));
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//add_config("terminationReference", str_or_n_value(cell->params, ctx->id("terminationReference"), "N"));
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//add_config("turbo", str_or_n_value(cell->params, ctx->id("turbo"), "N"));
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//add_config("weakTermination", str_or_n_value(cell->params, ctx->id("weakTermination"), "N"));
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close_instance();
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std::string tile_name = uarch->tile_name(cell->bel.tile);
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std::string bank = tile_name.substr(0, tile_name.rfind(':'));
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if (uarch->bank_voltage.count(bank)==0) {
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if (bank=="IOB0" || bank=="IOB1" || bank=="IOB6" || bank=="IOB7")
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uarch->bank_voltage[bank] = "3.3V";
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else
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uarch->bank_voltage[bank] = "1.8V";
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}
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}
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void write_dfr(CellInfo *cell) {
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open_instance(cell);
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//add_config("data_inv", bool_or_default(cell->params, ctx->id("data_inv"), false));
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//add_config("dff_edge", bool_or_default(cell->params, ctx->id("dff_edge"), false));
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//add_config("dff_init", bool_or_default(cell->params, ctx->id("dff_init"), false));
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//add_config("dff_load", bool_or_default(cell->params, ctx->id("dff_load"), false));
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//add_config("dff_sync", bool_or_default(cell->params, ctx->id("dff_sync"), false));
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//add_config("dff_type", bool_or_default(cell->params, ctx->id("dff_type"), false));
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//add_config("location", str_or_default(cell->params, ctx->id("location"), ""));
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add_config("mode", int_or_default(cell->params, ctx->id("mode"), 2));
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//add_config("path", int_or_default(cell->params, ctx->id("path"), 0));
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add_config("iobname", str_or_default(cell->params, ctx->id("iobname"), ""));
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if (cell->params.count(ctx->id("data_inv"))) {
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add_config("data_inv", bool_or_default(cell->params, ctx->id("data_inv"), false));
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}
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close_instance();
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}
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void write_cy(CellInfo *cell) {
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open_instance(cell);
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add_config("add_carry", int_or_default(cell->params, ctx->id("add_carry"), 0));
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add_config("shifter", bool_or_default(cell->params, ctx->id("shifter"), false));
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close_instance();
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}
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void write_fe(CellInfo *cell) {
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if (bool_or_default(cell->params, id_lut_used)) {
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open_instance_fe(cell, "LUT", ".LUT");
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add_config("lut_table", extract_bits_or_default(cell->params, id_lut_table, 16));
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close_instance();
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}
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if (bool_or_default(cell->params, id_dff_used)) {
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std::string subtype = str_or_default(cell->params, ctx->id("type"), "DFF");
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open_instance_fe(cell, subtype, ".DFF", "_D");
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if (subtype =="DFF") {
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add_config("dff_ctxt", std::to_string(int_or_default(cell->params, ctx->id("dff_ctxt"), 0)));
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add_config("dff_edge", bool_or_default(cell->params, ctx->id("dff_edge"), false));
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add_config("dff_init", bool_or_default(cell->params, ctx->id("dff_init"), false));
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add_config("dff_load", bool_or_default(cell->params, ctx->id("dff_load"), false));
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add_config("dff_sync", bool_or_default(cell->params, ctx->id("dff_sync"), false));
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add_config("dff_type", bool_or_default(cell->params, ctx->id("dff_type"), false));
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}
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close_instance();
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}
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}
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void write_iom(CellInfo *cell) {
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open_instance(cell);
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add_config("pads_path", str_or_default(cell->params, ctx->id("pads_path"), ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;"));
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close_instance();
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}
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void write_gck(CellInfo *cell) {
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open_instance(cell);
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add_config("inv_in", bool_or_default(cell->params, ctx->id("inv_in"), false));
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add_config("inv_out", bool_or_default(cell->params, ctx->id("inv_out"), false));
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add_config("std_mode", str_or_default(cell->params, ctx->id("std_mode"), "BYPASS"));
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close_instance();
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}
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void write_wfg(CellInfo *cell) {
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open_instance(cell);
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close_instance();
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}
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void write_rfb(CellInfo *cell) {
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open_instance(cell);
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add_config("context", str_or_default(cell->params, ctx->id("mem_ctxt"), ""));
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add_config("wck_edge", bool_or_default(cell->params, ctx->id("wck_edge"), false));
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close_instance();
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}
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void write_ram(CellInfo *cell) {
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open_instance(cell);
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add_config("mcka_edge", bool_or_default(cell->params, ctx->id("mcka_edge"), false));
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add_config("mckb_edge", bool_or_default(cell->params, ctx->id("mckb_edge"), false));
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add_config("pcka_edge", bool_or_default(cell->params, ctx->id("pcka_edge"), false));
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add_config("pckb_edge", bool_or_default(cell->params, ctx->id("pckb_edge"), false));
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add_config("raw_config0", extract_bits_or_default(cell->params, ctx->id("raw_config0"), 4));
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add_config("raw_config1", extract_bits_or_default(cell->params, ctx->id("raw_config1"), 16));
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add_config("context", str_or_default(cell->params, ctx->id("mem_ctxt"), ""));
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close_instance();
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}
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void write_interconnections()
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{
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for (auto &net : ctx->nets) {
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NetInfo *ni = net.second.get();
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if (ni->wires.size()==0) continue;
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std::vector<std::string> nets;
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for (auto &w : ni->wires) {
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if (w.second.pip != PipId()) {
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PipId pip = w.second.pip;
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const auto &pip_data = chip_pip_info(ctx->chip_info, w.second.pip);
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const auto &extra_data = *reinterpret_cast<const NGUltraPipExtraDataPOD *>(pip_data.extra_data.get());
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if (!extra_data.name or extra_data.type != PipExtra::PIP_EXTRA_INTERCONNECT) continue;
|
|
auto &pd = chip_pip_info(ctx->chip_info, pip);
|
|
IdString src = IdString(chip_tile_info(ctx->chip_info, pip.tile).wires[pd.src_wire].name);
|
|
std::string tile_name = uarch->tile_name(pip.tile);
|
|
std::string src_name = src.c_str(ctx);
|
|
std::string type = "OTC";
|
|
if (src_name.find("UI1x") != std::string::npos)
|
|
type = "ITC";
|
|
if (boost::starts_with(src_name,"SO1.")) type = "OTS";
|
|
if (boost::starts_with(src_name,"SI1.")) type = "ITS";
|
|
src_name = update_name(tile_name, src_name);
|
|
src_name = src_name.substr(0, src_name.size() - 2);
|
|
|
|
std::string name = cleanup_name(std::string(ni->name.c_str(ctx))+ "_" + src_name.substr(4));
|
|
out << stringf(",\n\t\t%s: {\n", get_string(name).c_str());
|
|
out << stringf("\t\t\t\"location\": %s,\n",get_string(tile_name + ":" + src_name).c_str());
|
|
out << stringf("\t\t\t\"type\": %s\n\t\t}",get_string(type).c_str());
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void write_instances()
|
|
{
|
|
out << "\t\"instances\": {\n";
|
|
first_instance = true;
|
|
for (auto &cell : ctx->cells) {
|
|
switch (cell.second->type.index) {
|
|
case id_BEYOND_FE.index: write_fe(cell.second.get()); break;
|
|
case id_IOP.index:
|
|
case id_IP.index:
|
|
case id_OP.index:
|
|
case id_IOTP.index:
|
|
case id_ITP.index:
|
|
case id_OTP.index: write_iop(cell.second.get()); break;
|
|
case id_CY.index: write_cy(cell.second.get()); break;
|
|
case id_WFB.index:
|
|
case id_WFG.index: write_wfg(cell.second.get()); break;
|
|
case id_GCK.index: write_gck(cell.second.get()); break;
|
|
case id_IOM.index: write_iom(cell.second.get()); break;
|
|
case id_BFR.index:
|
|
case id_DDFR.index:
|
|
case id_DFR.index: write_dfr(cell.second.get()); break;
|
|
case id_RAM.index: write_ram(cell.second.get()); break;
|
|
case id_RF.index:
|
|
case id_RFSP.index:
|
|
case id_XHRF.index:
|
|
case id_XWRF.index:
|
|
case id_XPRF.index: write_rfb(cell.second.get()); break;
|
|
//case id_XLUT.index:
|
|
//case id_FIFO.index:
|
|
//case id_XFIFO.index:
|
|
//case id_CDC.index:
|
|
//case id_XCDC.index:
|
|
//case id_CRX.index:
|
|
//case id_CTX.index:
|
|
//case id_DSP.index:
|
|
//case id_PLL.index:
|
|
//case id_PMA.index:
|
|
//case id_Service.index:
|
|
//case id_SOCIF.index:
|
|
default:
|
|
log_error("Unhandled cell %s of type %s\n", cell.second.get()->name.c_str(ctx), cell.second->type.c_str(ctx));
|
|
}
|
|
}
|
|
write_interconnections();
|
|
out << "\n\t},\n";
|
|
}
|
|
|
|
void write_setup()
|
|
{
|
|
out << "\t\"setup\": {\n";
|
|
out << "\t\t\"variant\": \"NG-ULTRA\",\n";
|
|
out << "\t\t\"iobanks\": {\n";
|
|
bool first = true;
|
|
for (auto &bank : uarch->bank_voltage) {
|
|
out << (first ? "" : ",\n");
|
|
out << stringf("\t\t\t%s:%s",get_string(bank.first).c_str(),get_string(bank.second).c_str());
|
|
first = false;
|
|
}
|
|
out << "\n\t\t}\n\t}\n";
|
|
}
|
|
|
|
void write_json()
|
|
{
|
|
out << "{\n";
|
|
write_nets();
|
|
write_instances();
|
|
write_setup();
|
|
out << "}\n";
|
|
}
|
|
};
|
|
|
|
} // namespace
|
|
|
|
void NgUltraImpl::write_bitstream_json(const std::string &filename)
|
|
{
|
|
std::ofstream out(filename);
|
|
if (!out)
|
|
log_error("failed to open file %s for writing (%s)\n", filename.c_str(), strerror(errno));
|
|
|
|
BitstreamJsonBackend be(ctx, this, out);
|
|
be.write_json();
|
|
}
|
|
|
|
NEXTPNR_NAMESPACE_END
|